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@inproceedings{TUW-222735,
    author = {Cilku, Bekim and Kammerer, Roland and Puschner, Peter},
    title = {Aligning Single Path Loops to Reduce the Number of Capacity Cache Misses},
    booktitle = {Proceedings of the 34th IEEE Real-Time Systems Symposium, 6th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems},
    year = {2013},
    url = {http://publik.tuwien.ac.at/files/PubDat_222735.pdf},
    keywords = {time predictability; cache memories; memory hierarchy; hard real-time systems;},
    note = {talk: 6th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems, Vancouver, Canada; 2013-12-03 -- 2013-12-06}
}


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