Publications in Scientific Journals

Authors: Markus Rupp, E389-02; Bernhard Wess, E389-03; Shuvra Bhattacharyya

M. Rupp, B. Wess, S. Bhattacharyya:
"Design Methods for DSP Systems";
EURASIP Journal on Applied Signal Processing, 2006 (2006), 1 - 3.

Authors: Thomas Zeitlhofer, E389-03; Bernhard Wess, E389-03

T. Zeitlhofer, B. Wess:
"List-coloring of interval graphs with application to register assignment for heterogeneous register-set architectures";
Signal Processing, 83 (2003), 1411 - 1425.

Author: Bernhard Wess, E389-03

B. Wess:
"Minimization of data address computation overhead in DSP programs";
Design Automation for Embedded Systems, 4 (1999), 167 - 185.

Authors: Werner Kreuzer; Stefan Fröhlich, E389-03; Martin Gotschlich, E389-03; Anton Helm, E389-03; Bernhard Wess, E389-03

W. Kreuzer, S. Fröhlich, M. Gotschlich, A. Helm, B. Wess:
"Übersetzung von Datenflußgraphen in optimierte Assemblerprogramme für Signalprozessoren";
E&I Elektrotechnik und Informationstechnik, 115 (1998), 41 - 47.


Talks and Poster Presentations (with Proceedings-Entry)

Authors: Thomas Zeitlhofer, E389-03; Bernhard Wess, E389-03

T. Zeitlhofer, B. Wess:
"Optimum Register and Functional Unit Assignment for VLIW DSPS: a Case Study";
Talk: GSPx & International Signal Processing Conference, Santa Clara, CA, USA; 10-24-2005 - 10-27-2005; in: "Conference Proceedings Pervasive Signal Processing", (2005), ISBN: 0-9728718-2-9; 6 pages.

Authors: Thomas Zeitlhofer, E389-03; Bernhard Wess, E389-03

T. Zeitlhofer, B. Wess:
"Integrated Assignment of Registers and Functional Units for Heterogeneous VLIW-Architectures";
Talk: IEEE International SOC Conference, Washington, USA; 09-25-2005 - 09-28-2005; in: "Proceedings IEEE International SOC Conference", (2005), ISBN: 0-7803-9264-7; 121 - 124.

Authors: Bernhard Wess, E389-03; Thomas Zeitlhofer, E389-03

B. Wess, T. Zeitlhofer:
"On the Phase Coupling Problem between Data Memory Layout Generation and Address Pointer Assignment";
Talk: International Workshop on Software and Compilers for Embedded Systems, Amsterdam, Niederlande; 09-02-2004 - 09-03-2004; in: "Proceedings of the 8th International Workshop on Software and Compilers for Embedded Systems, LNCS 3199", (2004), ISBN: 3-540-23035-1; 152 - 166.

Authors: Thomas Zeitlhofer, E389-03; Bernhard Wess, E389-03

T. Zeitlhofer, B. Wess:
"A Comparison of Graph Coloring Heuristics for Register Allocation Based on Coalescing in Interval Graphs";
Talk: IEEE International Symposium on Circuits and Systems, Vancouver; 05-23-2004 - 05-26-2004; in: "Proceedings of 2004 IEEE International Symposium on Circuits and Systems", (2004), ISBN: 0-7803-8251-x; 4 pages.

Authors: Bernhard Wess, E389-03; Thomas Zeitlhofer, E389-03

B. Wess, T. Zeitlhofer:
"Optimum Address Pointer Assignment for Digital Signal Processors";
Talk: IEEE Int. Conference on Acoustics, Speech, and Signal Processing (ICASSP), Montreal, Kanada; 05-17-2004 - 05-21-2004; in: "Proceedings of the 2004 IEEE Conference on Acoustics Speech and Signal Processing", (2004), ISBN: 0-7803-8485-7; Paper ID 0500121.PDF, 4 pages.

Authors: Thomas Zeitlhofer, E389-03; Bernhard Wess, E389-03

T. Zeitlhofer, B. Wess:
"Optimum register assignment for heterogeneous register-set architectures";
Talk: IEEE Int. Symposium on Circuits and Systems, Bangkok; 05-25-2003 - 05-28-2003; in: "ISCAS 2003", (2003), 252 - 255.

Authors: Thomas Zeitlhofer, E389-03; Robert Dallinger, E389-02; Bernhard Wess, E389-03

T. Zeitlhofer, R. Dallinger, B. Wess:
"Data register minimization for an application-specific DSP";
Talk: GSPx & International Signal Processing Conference, Dallas; 03-31-2003 - 04-03-2003; in: "ISPC Conference Proceedings", (2003), 1 - 6.

Authors: Stefan Fröhlich, E389-03; Bernhard Wess, E389-03

S. Fröhlich, B. Wess:
"Integrated Approach to Optimized Code Generation for Heterogeneous-Register Architectures with Multiple Data-Memory Banks";
Talk: Annual IEEE International ASIC/SOC Conference, Arlington, VA, USA; 09-12-2001 - 09-15-2001; in: "Proc. 14th Annual IEEE International ASIC/SOC Conference", (2001), 122 - 126.

Authors: Thomas Zeitlhofer, E389-03; Bernhard Wess, E389-03

T. Zeitlhofer, B. Wess:
"Integrated Scheduling and Registzer assignment for VLIW-DSP Architectures";
Talk: Annual IEEE International ASIC/SOC Conference, Arlington,VA,USA; 09-12-2001 - 09-15-2001; in: "14th Annual IEEE International ASIC/SOC Conference", (2001), 339 - 343.

Authors: Stefan Fröhlich, E389-03; Bernhard Wess, E389-03

S. Fröhlich, B. Wess:
"Optimizing Complex machine instructions with dynamic Trellis diagrams";
Talk: Int. Conference on Signal Processing Application & Technology, Dallas, TX, USA; 10-16-2000 - 10-19-2000; in: "Proc. ICSPAT 2000", (2000), 1 - 5.

Authors: Thomas Zeitlhofer, E389-03; Zrin Ziborski, E389-03; Bernhard Wess, E389-03

T. Zeitlhofer, Z. Ziborski, B. Wess:
"Assembly optimizer for the CARMEL TM DSP-Core";
Talk: Int. Conference on Signal Processing Application & Technology, Dallas, TX,USA; 10-16-2000 - 10-19-2000; in: "Proc. ICSPAT 2000", (2000), 1 - 5.

Author: Bernhard Wess, E389-03

B. Wess:
"Simulated evolutionary code generation for heterogeneous memory-register DSP-architectures";
Talk: EUSIPCO European Signal Processing Conference, Tampere, Finland; 09-04-2000 - 09-08-2000; in: "Signal Processing X", (2000), 2465 - 2468.

Authors: Bernhard Wess, E389-03; Thomas Zeitlhofer, E389-03

B. Wess, T. Zeitlhofer:
"Simulated evolutionary optimization of DSP programs";
Talk: Int. Conference on Signal Processing Application & Technology, Orlando, USA; 10-30-1999 - 11-06-1999; in: "Int. Conference on Signal Processing Application & Technology", CD-ROM (1999), 1 - 5.

Authors: Thomas Zeitlhofer, E389-03; Bernhard Wess, E389-03

T. Zeitlhofer, B. Wess:
"Code optimization for the CARMEL TM DSP-Core";
Talk: Int. Conference on Signal Processing Application & Technology, Orlando, USA; 10-30-1999 - 11-06-1999; in: "Int. Conference on Signal Processing Application & Technology (ICSPAT)", CD-ROM (1999), 1 - 5.

Authors: Stefan Fröhlich, E389-03; Martin Gotschlich, E389-03; Udo Krebelder, E389-03; Bernhard Wess, E389-03

S. Fröhlich, M. Gotschlich, U. Krebelder, B. Wess:
"Dynamic Trellis diagrams for optimized DSP code generation";
Talk: IEEE Int. Symposium on Circuits and Systems, Orlando, USA; 05-31-1999 - 06-02-1999; in: "IEEE Int. Symposium on Circuits and Systems (ISCAS'99)", (1999), 492 - 495.

Authors: Thomas Zeitlhofer, E389-03; Bernhard Wess, E389-03

T. Zeitlhofer, B. Wess:
"Operation scheduling for parallel functional units using genetic algorithms";
Talk: IEEE Int. Conference on Acoustics, Speech, and Signal Processing (ICASSP), Phoenix, AZ, USA; 03-15-1999 - 03-19-1999; in: "IEEE Int. Conference on Acoustics, Speech, and Signal Processing (ICASSP'99)", (1999), 1997 - 2000.

Authors: Bernhard Wess, E389-03; Stefan Fröhlich, E389-03

B. Wess, S. Fröhlich:
"DSP data memory layouts optimized for intermediate address pointer updates";
Talk: IEEE Asia-Pacific Conference on Circuits and Systems, Chiangmai, Thailand; 11-24-1998 - 11-27-1998; in: "IEEE Asia-Pacific Conference on Circuits and Systems 1998", (1998), 451 - 454.

Authors: Bernhard Wess, E389-03; Stefan Fröhlich, E389-03; Martin Gotschlich, E389-03

B. Wess, S. Fröhlich, M. Gotschlich:
"Optimization data ddress computation in DSP programs: Analysis and evaluation";
Talk: Int. Conference on Signal Processing Application & Technology, Toronto, Canada; 09-13-1998 - 09-16-1998; in: "9th Int. Conference on Signal Processing Application & Technology", (1998), 575 - 579.

Authors: Bernhard Wess, E389-03; Martin Gotschlich, E389-03

B. Wess, M. Gotschlich:
"Minimization of data address computation overhead in DSP programs";
Talk: IEEE Int. Conference on Acoustics, Speech, and Signal Processing (ICASSP), Seattle,WA, USA; 05-12-1998 - 05-15-1998; in: "IEEE Int. Conference on Acoustics, Speech, and Signal Processing (ICASSP'98)", (1998), 3093 - 3096.

Authors: Bernhard Wess, E389-03; Martin Gotschlich, E389-03

B. Wess, M. Gotschlich:
"Optimierungstechniken für Adreßrecheneinheiten in DSPs";
Talk: DSP Deutschland, München; 09-30-1997 - 10-01-1997; in: "DSP Deutschland", (1997), 25 - 34.

Authors: Bernhard Wess, E389-03; Martin Gotschlich, E389-03

B. Wess, M. Gotschlich:
"Code optimization techniques for DSPs with dedicated data address generation units";
Talk: Int. Conference on Signal Processing Application & Technology, San Diego, USA; 09-14-1997 - 09-17-1997; in: "Int. Conference on Signal Processing Application & Technology (ICSPAT'97)", (1997), 971 - 975.

Authors: Bernhard Wess, E389-03; Martin Gotschlich, E389-03

B. Wess, M. Gotschlich:
"Optimal DSP memory layout generation as a quadratic assignment problem";
Talk: IEEE Int. Symposium on Circuits and Systems, Honkong; 06-09-1997 - 06-12-1997; in: "IEEE Int.Symp. On Circuits and Systems (ISCAS'97)", (1997), 1712 - 1715.

Authors: Werner Kreuzer; Bernhard Wess, E389-03

W. Kreuzer, B. Wess:
"Cooperative register assignment and code compaction for digital signal processors with irregular datapaths";
Talk: IEEE Int. Conference on Acoustics, Speech, and Signal Processing (ICASSP), München; 04-21-1997 - 04-24-1997; in: "IEEE Int. Conference on Acoustics, Speech, and Signal Processing (ICASSP'97)", (1997), 691 - 694.

Authors: Bernhard Wess, E389-03; Martin Gotschlich, E389-03

B. Wess, M. Gotschlich:
"Constructing memory layouts for address generation units supporting offset 2 access";
Talk: IEEE Int. Conference on Acoustics, Speech, and Signal Processing (ICASSP), München; 04-21-1997 - 04-24-1997; in: "IEEE Int. Conference on Acoustics, Speech, and Signal Processing (ICASSP'97)", (1997), 683 - 686.

Authors: Martin Gotschlich, E389-03; Bernhard Wess, E389-03

M. Gotschlich, B. Wess:
"Automatic generation of constrained expression trees for global optimized DSP assembly code";
Talk: Int. Conference on Signal Processing Application & Technology, Boston, USA; 10-07-1996 - 10-10-1996; in: "Int. Conference on Signal Processing Application & Technology (ICSPAT'96)", (1996), 732 - 736.

Authors: Anton Helm, E389-03; Bernhard Wess, E389-03

A. Helm, B. Wess:
"A synchronous data flow graph compiler for telecommunication devices";
Talk: Int. Conference on Signal Processing Application & Technology, Boston, USA; 10-07-1996 - 10-10-1996; in: "Int. Conference on Signal Processing Application & Technology (ICSPAT'96)", (1996), 737 - 741.

Authors: Werner Kreuzer; Martin Gotschlich, E389-03; Bernhard Wess, E389-03

W. Kreuzer, M. Gotschlich, B. Wess:
"REDACO: A retargetable data flow graph compiler for digital signal processors";
Talk: Int. Conference on Signal Processing Application & Technology, Boston; 10-07-1996 - 10-10-1996; in: "Int. Conference on Signal Processing Application & Technology ICSPAT'96", (1996), 742 - 746.


Diploma and Master Theses (authored and supervised)

Author: Johannes Fürtler, E389
Other person involved: Bernhard Wess, E389-03

J. Fürtler:
"Entwicklungsumgebung zur visuellen Programmierung von Software-Pipelines";
Supervisor: B. Wess; Institut für Nachrichtentechnik und Hochfrequenztechnik, 2002.

Author: Mansour Baradaran-Hagh, E389
Other person involved: Bernhard Wess, E389-03

M. Baradaran-Hagh:
"Simulation zeitdiskreter Signalverarbeitungssysteme";
Supervisor: B. Wess; E 389, 1997.

Author: Manfred Eberl, E389
Other person involved: Bernhard Wess, E389-03

M. Eberl:
"Codegenerator für Signalprozessorfamilie TMS 320C5x";
Supervisor: B. Wess; E 389, 1997.

This publication list has been generated automatically from the publication data of the Faculty of Electrical Engineering and Information Technology. Please invoke the page "Publications of the Faculty" directly for more complex searches and queries, or use the global search function of the Publication Database of the Vienna University of Technology!