Publications in Scientific Journals
B. Knerr, M. Holzer, C. Angerer, M. Rupp:
"Slot-Wise Maximum Likelihood Estimation of the Tag Population Size in FSA Protocols";
IEEE Transactions on Communications,
58
(2010),
2;
578
- 585.
More information
B. Knerr, M. Holzer, M. Rupp:
"RRES: A Novel Approach to the Partitioning Problem for a Typical Subset of System Graphs";
EURASIP Journal on Embedded Systems,
2008
(2008),
1
- 13.
More information
P. Belanovic, B. Knerr, M. Holzer, M. Rupp:
"A Fully Automated Environment for Verification of Virtual Prototypes";
EURASIP Journal on Applied Signal Processing,
2006
(2006),
1
- 12.
More information
M. Holzer, B. Knerr, P. Belanovic, M. Rupp:
"Efficient Design Methods for Embedded Communication Systems";
EURASIP Journal on Embedded Systems,
2006
(2006),
ID 64913;
19 pages.
P. Belanovic, B. Knerr, M. Holzer, G. Sauzon, M. Rupp:
"A Consistent Design Methodology for Wireless Embedded Systems";
EURASIP Journal on Applied Signal Processing,
Vol. 2005
(2005),
16;
2598
- 2612.
Talks and Poster Presentations (with Proceedings-Entry)
M. Holzer, B. Knerr, C. Angerer, M. Rupp:
"Early Frame Restart in RFID Systems";
Talk: The Second International EURASIP Workshop on RFID Technology,
Budapest;
07-07-2008
- 07-08-2008; in: "The Second International EURASIP Workshop on RFID Technology",
(2008).
More information
B. Knerr, M. Holzer, C. Angerer, M. Rupp:
"Slot-by-slot Minimum Squared Error Estimator for Tag Populations in FSA Protocols";
Talk: The Second International EURASIP Workshop on RFID Technology,
Budapest;
07-07-2008
- 07-08-2008; in: "The 2nd Int. EURASIP Workshop on RFID Technology",
(2008),
1
- 13.
More information
B. Knerr, M. Holzer, C. Angerer, M. Rupp:
"Slot-by-slot Maximum Likelihood Estimation of Tag Populations in Framed Slotted Aloha Protocols";
Talk: 2008 International Symposium on Performance Evaluation of Computer and Telecommunication Systems (SPECTS),
Edinburgh, UK;
06-16-2008
- 06-18-2008; in: "2008 Int. Symposium on Performance Evaluation of Computer and Telecommunication Systems",
IEEE Catalog Number: CFP0874E
(2008),
ISBN: 1-56555-320-9;
303
- 308.
More information
C. Angerer, M. Holzer, B. Knerr, M. Rupp:
"A Flexible Dual Frequency Testbed for RFID";
Talk: Tridentcom08: 4th International Conference on Testbeds and Resarch Infrastructures for the Development of Networks & Communities,
Innsbruck;
03-18-2008
- 03-20-2008; in: "Tridentcom08: proceedings of the 4th International Conference on Testbeds and Research Infrastructures for the Development of Networks and Communities",
(2008),
ISBN: 978-1-60558-009-8.
More information
B. Knerr, M. Holzer, M. Rupp:
"Restricted Range Exhaustive Search: A New Heuristic for HW/SW Partitioning of Task Graphs";
Talk: Conference on Design of Circuits and Integrated Systems DCIS,
Sevilla, Spanien;
11-21-2007
- 11-23-2007; in: "Proceedings XXII Conference on Design of Circuits and Integrated Systems",
(2007),
ISBN: 978-84690-8629-2;
241
- 246.
More information
M. Holzer, B. Knerr, M. Rupp:
"Design Space Exploration for Real-Time Reconfigurable Computing";
Talk: Asilomar Conference on Signals, Systems, and Computers,
Pacific Grove, CA, USA (invited);
11-04-2007
- 11-07-2007; in: "Asilomar Conference on Signals, Systems, and Computers",
(2007),
ISBN: 9781424421107;
1981
- 1985.
More information
C. Angerer, B. Knerr, M. Holzer, A. Adalan, M. Rupp:
"Flexible Simulation and Prototyping for RFID Designs";
Talk: First International EURASIP Workshop on RFID Technology,
Wien;
09-24-2007
- 09-25-2007; in: "The first international EURASIP Workshop on RFID Technology, RFID 2007, Book of Proceedings",
P. Belanovic (ed.);
(2007),
ISBN: 3-902477-10-5;
51
- 54.
More information
M. Holzer, B. Knerr, M. Rupp:
"Design Space Exploration with Evolutionary Multi-Objective Optimisation";
Talk: IEEE Second International Symposium on Industrial Embedded Systems,
Lisbon, Portugal;
07-04-2007
- 07-06-2007; in: "2007 Symposium on Industrial Embedded Systems Proceedings",
(2007),
ISBN: 1-4244-0840-7;
126
- 133.
More information
B. Knerr, M. Holzer, M. Rupp:
"Novel Genome Coding of Genetic Algorithms for the System Partitioning Problem";
Talk: IEEE 2nd Symposium on Industrial Embedded Systems - SIES 2007,
Lissabon, Portugal;
07-04-2007
- 07-06-2007; in: "2007 Symposium on Industrial Embedded Systems Proceedings",
(2007),
ISBN: 1-4244-0840-7;
134
- 141.
More information
B. Knerr, M. Holzer, M. Rupp:
"Improvements Of The Gclp Algorithm For Hw/sw Partitioning Of Task Graphs";
Talk: Circuits, Systems and Signal Processing,
San Francisco, CA, USA;
11-20-2006
- 11-22-2006; in: "Proceedings of the 4th IASTED International Conference on Circuits, Systems, and Signals",
(2006),
ISBN: 0-88986-607-4;
107
- 113.
More information
M. Holzer, B. Knerr, M. Rupp:
"Structural Verification in Minimal Time";
Talk: International Symposium on System-on-Chip (SOC),
Tampere, Finnland;
11-14-2006
- 11-16-2006; in: "International Symposium on System-on-Chip",
(2006),
ISBN: 1-4244-0621-8;
151
- 154.
More information
M. Holzer, B. Knerr:
"Pareto Front Generation for a Tradeoff between Area and Timing";
Talk: Austrochip,
Messegelände Wien, Österreich;
10-11-2006; in: "Austrochip 2006 Tagungsband",
(2006),
ISBN: 3-200-00770-2;
131
- 134.
B. Knerr, M. Holzer, M. Rupp:
"Extending the GCLP Algorithm for HW/SW Partitioning: A Detailed Platform Model and Performance Improvements";
Talk: Austrochip,
Messezentrum Wien, Österreich;
10-11-2006; in: "Austrochip 2006 Tagungsband",
(2006),
ISBN: 3-200-00770-2;
89
- 95.
B. Knerr, M. Holzer, M. Rupp:
"A Fast Rescheduling Heuristic of SDF Graphs for HW/SW Partitioning Algorithms";
Talk: Conference on Communication System Software and Middleware (COMSWARE),
New Delhi, India;
01-08-2006
- 01-12-2006; in: "Proceedings of COMSWARE 2006",
(2006),
8 pages.
P. Belanovic, M. Holzer, B. Knerr, M. Rupp:
"Automated Verification Pattern Refinement for Virtual Prototypes";
Talk: Conference on Design of Circuits and Integrated Systems DCIS,
Lissabon, Portugal;
11-23-2005
- 11-25-2005; in: "Conference of Design of Circuits and Integrated Systems",
(2005),
6 pages.
B. Knerr, M. Holzer, M. Rupp:
"Fast Rescheduling of Multi-Rate Systems for HW/SW Partitioning Algorithms";
Talk: Asilomar Conference on Signals, Systems, and Computers,
Pacific Grove, CA, USA;
10-30-2005
- 11-02-2005; in: "Proceedings of Thirty-Ninth Annual Asilomar Conference on Signals, Systems, and Computers",
(2005),
ISBN: 1-4244-0132-1;
1375
- 1379.
More information
B. Knerr, M. Holzer, M. Rupp:
"Task Scheduling for Power Optimisation of Multi Frequency Synchronous Data Flow Graphs";
Talk: Annual Symposium on Integrated Circuits and System Design,
Florianapolis, Brazil;
09-04-2005
- 09-08-2005; in: "Proceedings of the 18th Annual Symposium on Integrated Circuits and System Design",
ACM Press,
(2005),
ISBN: 1-59593-174-0;
50
- 55.
M. Holzer, P. Belanovic, B. Knerr, M. Rupp:
"Automatic Design Techniques for Embedded Systems";
Talk: GI/ITG/GMM Workshop Modellierung und Verifikation,
Munich, Germany;
04-06-2005
- 04-07-2005; in: "Proceedings of GI/ITG/GMM Workshop Modellierung und Verifikation",
(2005),
10 pages.
B. Knerr, P. Belanovic, M. Holzer, G. Sauzon, M. Rupp:
"Design Flow Improvements for Embedded Wireless Receivers";
Talk: EUSIPCO European Signal Processing Conference,
Wien;
09-06-2004
- 09-10-2004; in: "EUSIPCO 2004 12th European Signal Processing Conference",
(2004),
ISBN: 3-200-00165-8;
2015
- 2018.
B. Knerr, M. Holzer, M. Rupp:
"HW/SW Partitioning Using High Level Metrics";
Talk: Int. Conference on Computer, Communication and Control Technologies, CCCT´04,
Austin, Texas (invited);
08-14-2004
- 08-17-2004; in: "Proceedings of the International Conference on Computing, Communications and Control Technologies",
vol. 7
(2004),
ISBN: 980-6560-18-3;
33
- 38.
B. Knerr, M. Holzer, P. Belanovic, G. Sauzon, M. Rupp:
"Advanced UMTS Receiver Chip Design Using Virtual Prototyping";
Talk: International Symposium on Signal, Systems, and Electronics (ISSSE),
Linz, Österreich;
08-10-2004
- 08-13-2004; in: "Proceedings of the 2004 International Symposium on Signals, Systems and Electronics ISSSE 04",
(2004).
M. Holzer, B. Knerr, P. Belanovic, M. Rupp, G. Sauzon:
"Faster Complex SoC Design by Virtual Prototyping";
Talk: International Conference on Cybernetics and Information Technologies, Systems and Applications (ISAS CITSA 2004),
Orlando, Florida;
07-21-2004
- 07-25-2004; in: "Proceedings of CITSA Internattional Conference on Cybernetics and Information Technologies, Systems and Applications",
(2004),
ISBN: 980-6560-20-5;
305
- 309.
P. Belanovic, M. Holzer, B. Knerr, M. Rupp, G. Sauzon:
"Automatic Generation of Virtual Prototypes";
Talk: IEEE International Workshop on Rapid System Prototyping (RSP),
Genf, Schweiz;
06-28-2004
- 06-30-2004; in: "Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping RSP 04",
(2004),
ISBN: 0-7695-2159-2;
114
- 118.
M. Holzer, P. Belanovic, B. Knerr, M. Rupp:
"Design Methodology for Signal Processing in Wireless Systems";
Talk: Informationstagung Mikroelektronik (ME),
Vienna;
10-01-2003
- 10-02-2003; in: "Informationstagung Mikroelektronik",
(2003),
303
- 307.
Talks and Poster Presentations (without Proceedings-Entry)
M. Rupp, B. Knerr, M. Holzer:
"Heuristic Optimisation Methods for System Partitioning in HW/SW Co-Design";
Talk: Technische Universität Madrid,
Madrid (invited);
10-06-2008.
Patents
M. Holzer, B. Knerr, P. Belanovic, M. Rupp, A. Häutle, C. Drewes, A. Sarahgi, G. Sauzon:
"Automatic Generation of Virtual Prototypes";
Patent: Europe,
submitted: 2004.
More information
Doctor's Theses (authored and supervised)
B. Knerr:
"Heuristic Optimisation Methods for System Partitioning in HW/SW Co-Design";
Supervisor, Reviewer: M. Rupp, C. Grimm;
Institut für Nachrichtentechnik und Hochfrequenztechnik,
2008;
oral examination: 07-22-2008.