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Scientific Reports:

B. Rahbaran:
"Performing Automatic Physical Injection of Signal-Flips and Delay Faults with the toolset FIDYCO";
Report for Research Report 46/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004.



English abstract:
As a result of increasing clock rates the timing margins are shrinking. This makes delay faults a remarkable source of failure. Delay faults, however, are extremely hard to find by tests. Therefore it is important to study their effects on system behavior by means of fault injection. At the same time the rate of transient faults is predicted to increase in the near future. With this motivation we propose a fault model comprising signal flips, transient stuck-at faults and delay faults. We motivate and illustrate our extended fault model and describe an implementation on an FPGA platform. Our approach allows a more detailed insight in a circuit's fault-tolerance than traditional models like the bit flip model or the permanent stuck-at model, while the use of our automated physical platform allows injecting a large number of faults within reasonable time. Results from practical fault injection experiments demonstrate the feasibility of our approach.


Electronic version of the publication:
http://www.vmars.tuwien.ac.at/php/pserver/docdetail.php?DID=1629&viewmode=paper&year=2004