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Talks and Poster Presentations (with Proceedings-Entry):

M. Birner, T. Handl:
"ARROW - A Generic Hardware Fault Injection Tool for NoCs";
Talk: DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece; 2009-08-27 - 2009-08-29; in: "12th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - Architectures, Methods and Tools - DSD 2009", IEEE Computer Society, (2009), ISBN: 978-0-7695-3782-5; 465 - 472.



English abstract:
Todays NoCs are reaching a level where it is getting
harder and harder to ensure 100 % of functionality. Fault
tolerance has become an important aspect in todays design
techniques and like the system itself, it has to be validated
and tested. A vulnerable point of attack for faults in com-
plex systems is certainly the interconnect. In this paper, we
will give an overview about todays challenges in intercon-
nect technology and potential resulting physical faults. By
mischance, the physical level is far too accurate and so it is
necessary to abstract and to map all these faults to a logical
level. In more complex systems, also the logical level may
become too detailed. As a result we have to introduce an
even more abstract layer, which is defined as the functional
level. To be able to verify fault tolerance, an experiment
based test approach with fault injection must be used. Ar-
row is a generic hardware fault injection tool, written in the
hardware description language VHDL, especially designed
for digital fault injection on the interconnect of NoCs, mak-
ing use of fault models from the logical level.

Keywords:
Fault Injection, Fault Tolerance, SoC, NoC, FPGA


"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
http://dx.doi.org/10.1109/DSD.2009.223