Talks and Poster Presentations (with Proceedings-Entry):
B. Cilku, R. Kammerer, P. Puschner:
"Aligning Single Path Loops to Reduce the Number of Capacity Cache Misses";
Talk: 6th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems,
Vancouver, Canada;
2013-12-03
- 2013-12-06; in: "Proceedings of the 34th IEEE Real-Time Systems Symposium, 6th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems",
(2013).
English abstract:
In this paper we address the problem of improving
the instruction cache performance for single-path code. The
properties of single-path code allow us to align single-path
loops within the cache in order to reduce the number of cache
misses during the loop execution. We propose an algorithm that
categorizes loops in a simple way so that the loops can be
aligned and NOP instructions can be inserted to support this
loop alignment. Our experimental results show the predictability
for cache misses in single-path loops and demonstrate the benefit
of the single-path loop alignment.
Keywords:
time predictability; cache memories; memory hierarchy; hard real-time systems;
Electronic version of the publication:
http://publik.tuwien.ac.at/files/PubDat_222735.pdf