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T. Polzer, R. Najvirt, F. Beck, A. Steininger:
"On the Appropriate Handling of Metastable Voltages in FPGAs";
Journal of Circuits, Systems, and Computers, 25 (2015), 3; 1640020-1 - 1640020-25.

The signi¯cant process, voltage and temperature (PVT) variations seen with modern technologies
make strictly synchronous design ine±cient. Asynchronous design with its °exible
timing is a promising alternative, but prototyping is di±cult on the available FPGA platforms
which are clock centric and do not provide the required functional primitives like mutual
exclusion or Muller C-elements. The solutions proposed in the literature so far work nicely in
principle but cannot safely handle metastability issues that are inevitable even at some interfaces
in asynchronous designs. In this paper, we propose reliable implementations of the fundamental
function blocks required to safely convert potential intermediate voltage levels that
result from metastability into late transitions that can be reliably handled in the asynchronous
domain. These are high- and low-threshold bu®ers as well as a Schmitt-trigger. We give elaborate
background analysis for the proposed circuits and also present the associated routing
constraints to make the Schmitt-trigger circuit work properly in spite of the uncertain routing
within FPGAs. Furthermore, we propose a procedure for an \in situ reliability assessment" of
the speci¯c Schmitt-trigger element under consideration, which also applies to metastability
containment with high- or low-threshold bu®ers only. Our proof of concept is based on experimental
results for both Xilinx and Altera FPGA platforms.

http://dx.doi.org/10.1142/S021812661640020X

http://publik.tuwien.ac.at/files/PubDat_246199.pdf