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M. Shafique, S. Garg, V. Chandra:
"Guest Editors´ Introduction: Computing in the Dark Silicon Era";
Ieee Design & Test, 34 (2017), 2; 3 pages.

In the Post-dennard´s scaling era of nanoscale CMOS devices, due to the slowdown of the supply voltage scaling, high integration of transistors per unit area leads to escalated trends of (local) power density and thermal profiles. Coupled with the physical limits imposed by device packaging and cooling technology on the peak power and peak power density, this results in the so-called "dark silicon problem." That is, a significant amount of computation, communication, and memory resources of an on-chip system cannot simultaneously be powered-on (at the peak performance level) for a given thermal design power (TDP) constraint and thus must stay "dark" (i.e., power-gated) or "dim" (i.e., in low-power states). The emergence of dark silicon introduces several new challenges on the design, architecture, and test communities concerning various design abstractions, for instance, how to best utilize the abundance of (potentially dark) transistors, both in terms of design time provisioning and runtime management, so as to improve quality metrics (such as performance and reliability) within peak power and thermal constraints.

http://dx.doi.org/10.1109/MDAT.2017.2651065