Talks and Poster Presentations (with Proceedings-Entry):
C. Fiedler, Franz Preyser, W. Kastner:
"Simulation of RPDEVS Models of Logic Gates";
Talk: ASIM Workshop STS/GMMS 2019,
Braunschweig;
2019-02-21
- 2019-02-22; in: "ASIM Workshop 2019 Simulation Technischer System Grundlagen und Methoden in Modellbildung und Simulation",
Arbeitsgemeinschaft Simulation ASIM in der Gesellschaft für Informatik GI,
ARGESIM Report 57
(2019),
ISBN: 978-3-901608-06-3;
129
- 134.
English abstract:
This paper addresses the simulation of fun-
damental logic gates (e.g. AND, OR, NOT) using the soft-
ware PowerRPDEVS that is based on the Revised Paral-
lel Discrete Event System Specification (RPDEVS) formalism.
The formal differences of the models of a NOR gate in
RPDEVS and PDEVS are analyzed. It is further shown,
which possible pitfalls may occur when connecting these
logic gates with feedbacks that cause algebraic loops and
in which cases these algebraic loops are resolved by the
RPDEVS simulation algorithm. For this purpose a static
RS flip-flop, a triggered D flip-flop and a shift register are
modeled and simulated in PowerRPDEVS. The results are
compared to previous research about the simulation of
such logic circuits in Simulink and Modelica.
Keywords:
Modeling and Simulation, RPDEVS, PowerRPDEVS, Logic Simulation,
"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
http://dx.doi.org/10.11128/arep.57
Electronic version of the publication:
https://publik.tuwien.ac.at/files/publik_285174.pdf