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208 matching records have been found with your search parameters:
187 - Faculty of Informatics
21 - Faculty of Electrical Engineering and Information Technology

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Zeitschriftenartikel:


  1. Source: Faculty of Informatics

    E. Armengaud, A. Steininger, M. Horauer:
    "Towards a Systematic Test for Embedded Automotive Communication Systems";
    IEEE Transactions on Industrial Informatics, 4 (2008), 3; 145 - 208.

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  2. Source: Faculty of Informatics

    P. Behal, F. Huemer, R. Najvirt, A. Steininger, Z. Tabassam:
    "Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles";
    TCVLSI Newsletter (invited), 7 (2021), 4; 1 pages.

  3. Source: Faculty of Informatics

    D. Dolev, M Függer, C. Lenzen, U. Schmid, A. Steininger:
    "Fault-tolerant Distributed Systems in Hardware";
    Bulletin of the EATCS, 2 (2015), 116; 43 pages.

  4. Source: Faculty of Informatics

    D. Dolev, M Függer, M. Posch, U. Schmid, A. Steininger, C. Lenzen:
    "Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip";
    Journal of Computer and System Sciences, 80 (2014), 4; 860 - 900.

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  5. Source: Faculty of Informatics

    W. Dür, M. Függer, A. Steininger:
    "Generation of a fault-tolerant clock through redundant crystal oscillators";
    Microelectronics Reliability, 120 (2021), 11 pages.

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  6. Source: Faculty of Informatics

    M Függer, A. Steininger, E. Armengaud:
    "Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - A Combined Formal and Experimental Approach";
    IEEE Transactions on Industrial Informatics, 5 (2009), 2; 132 - 145.

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  7. Source: Faculty of Electrical Engineering and Information Technology

    M. Hofbauer, K. Schweiger, H. Dietrich, H. Zimmermann, K.O. Voss, B Merk, U. Schmid, A. Steininger:
    "Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating Through a 90 nm Bulk CMOS Inverter Chain";
    IEEE Transactions on Nuclear Science, vol 59 (2012), 2778 - 2784.

  8. Source: Faculty of Informatics

    M. Hofbauer, K. Schweiger, H. Zimmermann, U. Giesen, F. Langner, U. Schmid, A. Steininger:
    "Supply Voltage Dependent On-Chip Single-Event Transient Pulse Shape Measurements in 90-nm Bulk CMOS Under Alpha Irradiation";
    IEEE Transactions on Nuclear Science, 60 (2013), 4; 2640 - 2646.

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  9. Source: Faculty of Informatics

    F. Huemer, A. Steininger:
    "Novel Approaches for Efficient Delay-Insensitive Communication";
    Journal of Low Power Electronics and Applications, 9 (2019), 16; 41 pages.

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  10. Source: Faculty of Informatics

    J. Maier, C. Hartl-Nesic, A. Steininger:
    "Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses";
    IEEE Transactions on Circuits and Systems-I: Regular Papers, Dec (2021), 1 - 14.

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  11. Source: Faculty of Informatics

    T. Polzer, F. Huemer, A. Steininger:
    "An Experimental Study of Metastability-Induced Glitching Behavior";
    Journal of Circuits, Systems, and Computers, 28 (2019), Suppl 1; 21 pages.

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  12. Source: Faculty of Informatics

    T. Polzer, F. Huemer, A. Steininger:
    "Refined Metastability Characterization Using a Time-to-Digital Converter";
    Microelectronics Reliability, 80 (2018), 91 - 99.

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  13. Source: Faculty of Informatics

    T. Polzer, R. Najvirt, F. Beck, A. Steininger:
    "On the Appropriate Handling of Metastable Voltages in FPGAs";
    Journal of Circuits, Systems, and Computers, 25 (2015), 3; 1640020-1 - 1640020-25.

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  14. Source: Faculty of Informatics

    T. Polzer, A. Steininger:
    "A Model for the Metastability Delay of Sequential Elements";
    Journal of Circuits, Systems, and Computers, 26 (2017), 8; 174001001 - 174001022.

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  15. Source: Faculty of Informatics

    B. Rahbaran, M Függer, A. Steininger:
    "Embedded Real-Time-Tracer -- An Approach with IDE";
    Telematik, 3-4 (2004), 16 - 20.

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  16. Source: Faculty of Informatics

    B. Rahbaran, A. Steininger:
    "Is Asynchronous Logic More Robust Than Synchronous Logic?";
    IEEE Transactions on Dependable and Secure Computing, 6 (2009), 4; 282 - 294.

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  17. Source: Faculty of Informatics

    T. Reinbacher, J. Brauer, M. Horauer, A. Steininger, S. Kowalewski:
    "Runtime verification of microcontroller binary code";
    Science of Computer Programming, 80 (2014), 109 - 129.

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  18. Source: Faculty of Informatics

    S. Resch, A. Steininger, C. Scherrer:
    "A Composable Real-Time Architecture for Replicated Railway Applications";
    Journal of Systems Architecture, 61 (2015), 9; 472 - 485.

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  19. Source: Faculty of Informatics

    C. Scherrer, A. Steininger:
    "Dealing With Dormant Faults in an Embedded Fault-Tolerant Computer System";
    IEEE Transactions on Reliability, 52 (2003), 4; 512 - 522.

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  20. Source: Faculty of Electrical Engineering and Information Technology

    C. Scherrer, A. Steininger:
    "Vom Lenkrad zum Joystick";
    E&I Elektrotechnik und Informationstechnik, vol. 117 (2000), 714 - 720.

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  21. Source: Faculty of Electrical Engineering and Information Technology

    C. Scherrer, A. Steininger et al.:
    "Assessment of Computer Fault Tolerance - A Fault-Injection Toolset an the Rationale behind It";
    Computer Standards and Interfaces, vol 21, oct (1999), 357 - 369.

  22. Source: Faculty of Informatics

    U. Schmid, A. Steininger, M. Sust:
    "FIT-IT Projekt DARTS: Dezentrale fehlertolerante Taktgenerierung";
    Elektrotechnik und Informationstechnik (e&i), Heft 1-2 (2007), 3 - 8.

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  23. Source: Faculty of Electrical Engineering and Information Technology

    A. Steininger et al.:
    "Protokollierung und Auswertung von Meßdaten in Echtzeit mit dem PC am Beispiel der Materialprüfung";
    TM - Technisches Messen, 1 (1997), 12 - 20.

  24. Source: Faculty of Informatics

    A. Steininger:
    "Testing and Built-in-Self-Test - A Survey";
    Journal of Systems Architecture, 46 (2000), 721 - 747.

  25. Source: Faculty of Informatics

    A. Steininger, G. Fuchs:
    "VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation";
    Journal of Electrical and Computer Engineering, Clock/Frequency Generation Circuits and Systems (2011), 936712; 23.

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  26. Source: Faculty of Electrical Engineering and Information Technology

    A. Steininger, Ch. Mittermayer:
    "On the Determination of Dynamic Errors for Rise Time Measurement With an Oscilloscope";
    IEEE Transactions on Instrumentation and Measurement, vol 48, issue 6 (1999), 1003 - 1007.

  27. Source: Faculty of Informatics

    A. Steininger, C. Scherrer:
    "Identifying Efficient Combinations of Error Detection Mechanisms Based on Results of Fault-Injection Experiments";
    IEEE Transactions on Computers, 51 (2002), 2; 235 - 239.

  28. Source: Faculty of Informatics

    A. Steininger, C. Scherrer:
    "Vom Lenkrad zum Joystick";
    Elektrotechnik und Informationstechnik (e&i), 11 (2000), 714 - 720.

  29. Source: Faculty of Informatics

    A. Steininger, P Tummeltshammer:
    "Replicated processors on a single die - How independently do they fail?";
    Journal e&i: Elektrotechnik und Informationstechnik, 128 (2011), 245 - 250.

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  30. Source: Faculty of Electrical Engineering and Information Technology

    A. Steininger, H. Zimmermann, A. Jantsch, M. Hofbauer, U. Schmid, K. Schweiger, V. S. Veeravalli:
    "Building reliable systems-on-chip in nanoscale technologies";
    E&I Elektrotechnik und Informationstechnik, 132 (2015), 6; 301 - 306.

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  31. Source: Faculty of Informatics

    K. Thaller, A. Steininger:
    "A Transparent Online Memory Test for Simultaneous Detection of Functional Faults and Soft Errors in Memories";
    IEEE Transactions on Reliability, 52 (2003), 4; 413 - 422.

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  32. Source: Faculty of Informatics

    V. S. Veeravalli, T. Polzer, U. Schmid, A. Steininger, M. Hofbauer, K. Schweiger, H. Dietrich, K. Schneider-Hornstein, H. Zimmermann, K. Voss, B. Merk, M. Hajek:
    "An infrastructure for accurate characterization of single-event transients in digital circuits";
    Microprocessors and Microsystems, 37 (2013), 772 - 791.

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  33. Source: Faculty of Informatics

    V. S. Veeravalli, A. Steininger, U. Schmid:
    "A versatile architecture for long-term monitoring of single-event transient durations";
    Microprocessors and Microsystems, 53 (2017), C; 130 - 144.

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Editorials in wiss. Zeitschriften:


  1. Source: Faculty of Informatics

    M. Krstic, I. Jones, A. Steininger, M Függer:
    "Special Issue "Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018"";
    Journal of Low Power Electronics and Applications, 9 (2019), 2; 2 pages.

  2. Source: Faculty of Informatics

    A. Steininger, A. Pawlak, V. Stopjakova:
    "Novel Trends in Design & Test";
    Journal of Circuits, Systems, and Computers, 26 (2017), 80 pages.


Buchbeiträge:


  1. Source: Faculty of Electrical Engineering and Information Technology

    L. Gurtner, A. Steininger:
    "Digitale Zählerbausteine";
    in: "Elektrische Meßtechnik", R. Patzelt, H. Schweinzer (ed.); Springer-Verlag, 1996, ISBN: 3-211-82873-7, 235 - 238.

  2. Source: Faculty of Electrical Engineering and Information Technology

    Ch. Mittermayer, A. Steininger:
    "Meßgrößen-Bewertung, Diskriminator, Schwellwertschalter, Schwellwertverstärker";
    in: "Elektrische Meßtechnik", R. Patzelt, H. Schweinzer (ed.); Springer-Verlag, 1996, ISBN: 3-211-82873-7, 226 - 234.

  3. Source: Faculty of Electrical Engineering and Information Technology

    R. Patzelt, A. Steininger:
    "Analogszilloskopie";
    in: "Elektrische Meßtechnik", R. Patzelt, H. Schweinzer (ed.); Springer-Verlag, 1996, ISBN: 3-211-82873-7, 395 - 414.

  4. Source: Faculty of Informatics

    J. Reisinger, A. Steininger, G. Leber:
    "The Implementation of the MARS Hardware and Software";
    in: "Predicatbly Dependable Computing Systems", B. Randell, J. Laprie, H. Kopetz, B. Littlewood (ed.); issued by: ESPRIT Basic Research Series; Springer International Publishing, 1995, ISBN: 3-540-59334-9, 209 - 224.

  5. Source: Faculty of Informatics

    A. Steininger:
    "Fifty Shades of Synchrony";
    in: "This Asynchronous Woirld", A. Mokhov (ed.); Newcastle University, Newcastle upon Tyne, 2016, (invited), ISBN: 978-0-7017-0257-1, 294 - 300.

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  6. Source: Faculty of Electrical Engineering and Information Technology

    A. Steininger:
    "Zeit-und Frequenzmessung";
    in: "Elektrische Meßtechnik", R. Patzelt, H. Schweinzer (ed.); Springer-Verlag, 1996, ISBN: 3-211-82873-7, 376 - 385.

  7. Source: Faculty of Electrical Engineering and Information Technology

    A. Steininger, R. Ertl:
    "Meßgeräte, Meßmethoden";
    in: "Elektrische Meßtechnik", R. Patzelt, H. Schweinzer (ed.); Springer-Verlag, 1996, ISBN: 3-211-82873-7, 291 - 328.


Beiträge in Tagungsbänden:


  1. Source: Faculty of Informatics

    E. Armengaud, F Rothensteiner, A. Steininger, R. Pallierer, M. Horauer, M Zauner:
    "A Structured Approach for the Systematic Test of Embedded Automotive Communication Systems";
    in: "Proceedings International Test Conference 2005", IEEE Computer Society, 2005, ISBN: 0-7803-9039-3, 21 - 28.

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  2. Source: Faculty of Informatics

    F. Huemer, T. Polzer, A. Steininger:
    "Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA";
    in: "2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)", issued by: IEEE CS Press; IEEE Xplore Digital Library, 2018, ISBN: 978-1-5386-5754-6, 141 - 146.

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  3. Source: Faculty of Informatics

    F. Huemer, A. Steininger:
    "Advanced Delay-Insensitive 4-Phase Protocols";
    in: "2018 Austrochip Workshop on Microelectronics (Austrochip)", issued by: IEEE CS Press; IEEE Xplore Digital Library, 2018, ISBN: 978-1-5386-8200-5, 50 - 55.

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  4. Source: Faculty of Informatics

    F. Huemer, A. Steininger:
    "Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication";
    in: "2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)", issued by: IEEE CS Press; IEEE Xplore Digital Library, 2018, ISBN: 978-1-5386-5883-3, 17 - 25.

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  5. Source: Faculty of Informatics

    R. Pallierer, M. Horauer, M Zauner, A. Steininger, E. Armengaud, F Rothensteiner:
    "A Generic Tool for Systematic Tests in Embedded Automotive Communication Systems";
    in: "Embedded World 2005", unbekannt, 2005.

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  6. Source: Faculty of Informatics

    M. Schütz, A. Steininger, F. Huemer, J. Lechner:
    "State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration";
    in: "2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)", issued by: IEEE CS Press; IEEE Xplore Digital Library, 2018, ISBN: 978-1-5386-8398-9, 6 pages.

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Editorials in Tagungsbänden:


  1. Source: Faculty of Informatics

    E. Brunvand, K. Stevens, M. Moreira, A. Steininger:
    "Welcome Message: ASYNC 2020";
    in: "Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)", IEEE Computer Society, 2020, (invited), ISBN: 978-1-7281-5495-4, 2 pages.

  2. Source: Faculty of Informatics

    L. Sekanina, M. Shafique, M. Krstic, A. Steininger, G. Stojanovic:
    "Foreword";
    in: "Proceedings 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", IEEE, 2021, (invited), ISBN: 978-1-6654-3595-6, 1 pages.


Vorträge und Posterpräsentationen (mit Tagungsband-Eintrag):


  1. Source: Faculty of Informatics

    K. Ambrosch, M. Humenberger, W. Kubinger, A. Steininger:
    "Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras";
    Talk: IEEE Conference on Computer Vision and Pattern Recognition, 2008. CVPR '08, Anchorage, Alaska, USA; 2008-06-23 - 2008-06-28; in: "CVPR Workshops 2008. IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, 2008.", (2008), ISBN: 978-1-4244-2339-2; 1 - 8.

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  2. Source: Faculty of Informatics

    K. Ambrosch, M. Humenberger, W. Kubinger, A. Steininger:
    "Hardware Implementation of an SAD based stereo vision algorithm";
    Talk: Third IEEE Workshop on Embedded Computer Vision, Minneapolis; 2007-06-23; in: "Proceedings of Third IEEE Workshop on Embedded Computer Vision", (2007).

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  3. Source: Faculty of Informatics

    M. Andjelkovic, M. Krstic, R. Kraemer, V. S. Veeravalli, A. Steininger:
    "A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study";
    Talk: The 26th IEEE Asian Test Symposium (ATSī17), Taipei, Taiwan; 2017-11-27 - 2017-11-30; in: "Proceedings of the 26th IEEE Asian Test Symposium (ATSī17)", (2017), 1 - 6.

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  4. Source: Faculty of Informatics

    L. Anghel, V. S. Veeravalli, D. Alexandrescu, A. Steininger, K. Schneider, E. Costenaro:
    "Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum";
    Talk: 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10), Stanford University, USA; 2014-04-01 - 2014-04-02; in: "Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10)", (2014), 6 pages.

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  5. Source: Faculty of Informatics

    E. Armengaud, M Függer, A. Steininger:
    "Safe deterministic replay for stimulating the clock synchronization algorithm in time-triggered systems";
    Talk: WFCS, Dresden, Germany; 2008-05-20 - 2008-05-23; in: "IEEE International Workshop on Factory Communication Systems, 2008. WFCS 2008.", (2008), ISBN: 978-1-4244-2349-1; 277 - 286.

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  6. Source: Faculty of Informatics

    E. Armengaud, F Rothensteiner, A. Steininger, M. Horauer:
    "A Flexible Hardware Architecture for Fast Access on Large Non-Volatile Memories";
    Talk: IEEE International Workshop on Desgin & Diagnostic of Electronic Circuits and Systems, Sopron; 2005-04-13 - 2005-04-16; in: "Proceedings of IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS) 2005", (2005), 113 - 120.

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  7. Source: Faculty of Informatics

    E. Armengaud, A. Steininger:
    "A Remote and Transparent Approach for the Test and Diagnosis of Automotive Networks";
    Poster: Junior Scientist Conference, Wien; 2006-04-19 - 2006-04-21; in: "Junior Scientist Conference 2006", (2006).

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  8. Source: Faculty of Informatics

    E. Armengaud, A. Steininger:
    "Automatic Parameter Identification in FlexRay Based Automotive Communication Networks";
    Talk: IEEE International Conference on Emerging Technologies and Factory Automation, Prag; 2006-09-20 - 2006-09-22; in: "11th IEEE International Conference on Emerging Technologies and Factory Automation", (2006), 897 - 904.

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  9. Source: Faculty of Informatics

    E. Armengaud, A. Steininger:
    "Pushing the Limits of Remote Online Diagnosis in FlexRay Networks";
    Talk: IEEE International Workshop on Factory Communication Systems, Torino; 2006-06-27 - 2006-06-30; in: "6th IEEE International Workshop on Factory Communication Systems", (2006).

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  10. Source: Faculty of Informatics

    E. Armengaud, A. Steininger:
    "Remote Measurement of Local Oscillator Drifts in FlexRay Networks";
    Talk: DATE 2009 (Design, Automation and Test in Europe), Nice, France; 2009-04-20 - 2009-04-24; in: "DATE09", Springer, (2009), ISBN: 9783981080155; 1082 - 1087.

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  11. Source: Faculty of Informatics

    E. Armengaud, A. Steininger, A. Hanzlik:
    "The Effect of Quartz Drift on Convergence-Average based Clock Synchronization";
    Talk: IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), Patras; 2007-09-25 - 2007-09-28; in: "Proceedings of the 12th IEEE Conference on Emerging Technologies and Factory Automation", (2007), 1123 - 1130.

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  12. Source: Faculty of Informatics

    E. Armengaud, A. Steininger, M. Horauer:
    "A Method for Bit Level Test and Diagnosis of Communication Services";
    Talk: IEEE International Workshop on Desgin & Diagnostic of Electronic Circuits and Systems, Sopron; 2005-04-13 - 2005-04-16; in: "Proceedings of IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS) 2005", (2005), 69 - 74.

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  13. Source: Faculty of Informatics

    E. Armengaud, A. Steininger, M. Horauer:
    "An Efficient Test and Diagnosis Environment for Communication Controllers";
    Talk: Austrochip, Wien; 2005-10-06; in: "Austrochip 2005", ???, (2005).

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  14. Source: Faculty of Informatics

    E. Armengaud, A. Steininger, M. Horauer:
    "Efficient Stimulus Genereation for Remote Testing of Distributed Systems - The Flexray Example";
    Talk: ETFA, Catania, Italy; 2005-09-19 - 2005-09-22; in: "Proceedings of the 10th IEEE Internationla Conference on Emerging Technologies and Factory Automation", IEEE, I (2005), 763 - 770.

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  15. Source: Faculty of Informatics

    E. Armengaud, A. Steininger, M. Horauer, R. Pallierer:
    "A Layer Model for the Systematic Test of Time-Triggered Automotive Communication Systems";
    Talk: IEEE International Workshop on Factory Communication Systems, Vienna,Austria; 2004-09-22 - 2004-09-24; in: "IEEE Workshop on Factory Communication Systems (WFCS 04)", IEEE Catalog Number 04TH8777 (2004), ISBN: 0-7803-8734-1; 275 - 283.

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  16. Source: Faculty of Informatics

    E. Armengaud, A. Steininger, M. Horauer, R. Pallierer:
    "Design Trade-offs for Systematic Tests of Embedded Communication Systems";
    Talk: IEEE International Conference on Dependable Systems and Networks, Florence, Italy; 2004-07-28 - 2004-08-01; in: "International Conference on Dependable Systems and Networks (DSN 2004)", (2004), 118 - 119.

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  17. Source: Faculty of Informatics

    E. Armengaud, A. Steininger, M. Horauer, R. Pallierer, H. Friedl:
    "A Monitoring Concept for an Automotive Distributed Network - The FlexRay Example";
    Talk: 7th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2004), Stara Lesna, Slovakia; 2004-04-18 - 2004-04-21; in: "Proceedings of the 7th Workshop on Design and Diognostics of Electronic Circuits and Systems", (2004), ISBN: 80-969117-9-1; 173 - 178.

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  18. Source: Faculty of Informatics

    P. Behal, F. Huemer, R. Najvirt, A. Steininger:
    "An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits";
    Talk: 24th Euromicro Conference on Digital System Design, Palermo, Italy; 2021-09-01 - 2021-09-03; in: "Proceedings of the 24th Euromicro Conference on Digital System Design", (2021), 1 - 8.

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  19. Source: Faculty of Informatics

    P. Behal, F. Huemer, R. Najvirt, Z. Tabassam, A. Steininger:
    "Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles";
    Talk: 27th IEEE International Symposium on Asynchronous Circuits and Systems, online; 2021-09-07 - 2021-09-10; in: "Proceedings 27th IEEE International Symposium on Asynchronous Circuits and Systems", (2021), 1 - 8.

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  20. Source: Faculty of Informatics

    M. Delvai, C. El Salloum, A. Steininger:
    "A Generic Real-time Debugger Architecture";
    Talk: World Multiconference on Systemics, cybernetics and Informatics, Orlando, Florida; 2003-07-27 - 2003-07-30; in: "The 7th World Multiconference on Systemics, Cybernetics and Informatics", (2003), 65 - 70.

  21. Source: Faculty of Informatics

    M. Delvai, G. Fuchs, T. Handl, W. Huber, A. Steininger:
    "Design of an Asynchronous Microprocessor with Four-State Logic";
    Talk: Austrochip, Wien; 2005-10-06; in: "Austrochip 2005", (2005), 105 - 112.

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  22. Source: Faculty of Informatics

    M. Delvai, W. Huber, P. Puschner, A. Steininger:
    "Processor Support for Temporal Predictability - The SPEAR Design Example";
    Talk: 15th Euromicro Conference on Real-Time Systems, Porto, Portugal; 2003-07-02 - 2003-07-04; in: "Proceedings of the 15 Euromicro International Conference on Real-Time Systems", (2003), 169 - 176.

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  23. Source: Faculty of Informatics

    M. Delvai, W. Huber, B. Rahbaran, A. Steininger:
    "An FPGA-Based Development Platform for the virtual Real-Time Processor Component SPEAR";
    Talk: IEEE Design and Diagnostics of Electronic Circuits and Systems (IEEE DDECS 2002), Brno, Czech Republic; 2002-04-17 - 2002-04-19; in: "Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop", (2002), 98 - 105.

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  24. Source: Faculty of Informatics

    M. Delvai, W. Huber, B. Rahbaran, A. Steininger:
    "SPEAR-Design-Entscheidungen für den "Scalable Processor for Embeded Application in Real-Time Environment"";
    Talk: Austrochip, wien; 2001-10-12; in: "Die Österreichische Tagnung zum Themenbereich Mikroelektronik", (2001), 25 - 32.

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  25. Source: Faculty of Informatics

    M. Delvai, M. Jankela, A. Steininger:
    "Towards Virtual Prototyping of Embedded Computer Systems";
    Poster: The 7th World Multiconference on Systemics, Cybernetics and Informatics, Orlando, Florida; 2003-07-27 - 2003-07-30; in: "Proceedings, Volume I, Information Systems, Technologies and Applications", (2003), 70 - 75.

  26. Source: Faculty of Informatics

    M. Delvai, A. Steininger:
    "A Practical Comparison of Logic Design Styles";
    Talk: The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications, Orlando; 2006-07-20 - 2006-07-23; in: "The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications - Volume 3", (2006), 61 - 66.

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  27. Source: Faculty of Informatics

    M. Delvai, A. Steininger:
    "Asynchronous Logic Design - from Concepts to Implementation";
    Talk: The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications, Orlando; 2006-07-20 - 2006-07-23; in: "The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications - Volume 1", (2006), 81 - 86.

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  28. Source: Faculty of Informatics

    M. Delvai, A. Steininger:
    "Solving the Fundamental Problem of Digital Design -- A Systematic Review of Design Methods";
    Poster: 9th Euromicro Conference on Digital System Design, Dubrovnik; 2006-08-30 - 2006-09-01; in: "9th Euromicro Conference on Digital System Design - Architectures, Methods and Tools", (2006), 131 - 136.

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  29. Source: Faculty of Informatics

    M. Delvai, A. Steininger:
    "Teaching Hardware Software Codesign to Software Engineers";
    Talk: 1st International Workshop on Reconfigurable Computing Education, Karlsruhe; 2006-03-01; in: "International Workshop on Reconfigurable Computing Education", (2006).

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  30. Source: Faculty of Informatics

    W. Dür, A. Steininger:
    "Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock";
    Talk: 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Novi Sad; 2020-04-22 - 2020-04-24; in: "Proceedings 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", Ieee Cs, (2020), 1 - 6.

  31. Source: Faculty of Informatics

    C. El Salloum, A. Steininger, P Tummeltshammer:
    "Recovery Mechanisms for Dual Core Architectures";
    Talk: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT ), Washington DC, USA; 2006-10-04 - 2006-10-06; in: "21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006, Proceedings", (2006), ISBN: 0-7695-2706-x; 380 - 388.

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  32. Source: Faculty of Informatics

    R. El Shahaby, A. Steininger:
    "Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines";
    Talk: 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Wien; 2021-04-07 - 2021-04-09; in: "Proceedings 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", Ieee Cs, (2021), ISBN: 978-1-6654-3595-6; 1 - 6.

  33. Source: Faculty of Informatics

    R. El Shahaby, A. Steininger:
    "On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective";
    Talk: IEEE International Conference on Computer Design, Hartford, Connecticut, USA; 2020-10-18 - 2020-10-21; in: "Proceedings IEEE International Conference on Computer Design", (2020), 1 - 4.

  34. Source: Faculty of Informatics

    M. Ferringer, G. Fuchs, A. Steininger, G. Kempf:
    "VLSI Implementation of a Fault-Tolerant Distributed Clock Generation";
    Talk: International Symp. on Defect and Fault Tolerance in VLSI-Systems, Arlington; 2006-10-04 - 2006-10-06; in: "The 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems", (2006), 563 - 571.

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  35. Source: Faculty of Informatics

    W. Forster, C. Kutschera, A. Steininger, K. Göschka:
    "Automated Generation of Explicit Connectors for Component Based Hardware/Software Interaction in Embedded Real-Time Systems";
    Talk: 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS 2008), (IPDPS 2008), Miami, Florida, USA; 2008-04-14; in: "Proceedings of the 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS 2008), (IPDPS 2008)", IEEE Computer Society, (2008), ISBN: 978-1-4244-1694-3; 1 - 8.

  36. Source: Faculty of Informatics

    W. Friesenbichler, T. Panhofer, A. Steininger:
    "A Deterministic Approach for Hardware Fault Injection in Asynchronous QDI Logic";
    Talk: DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria; 2010-04-14 - 2010-04-16; in: "13th IEEE International Symposium On Design And Diagnostics Of Electronic Cicruits And Systems", IEEE, (2010), ISBN: 9781424466108; 317 - 322.

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  37. Source: Faculty of Informatics

    W. Friesenbichler, T. Panhofer, A. Steininger:
    "Implementation of Self-Healing Asynchronous Circuits at the Example of a Video-Processing Algorithm";
    Talk: WSDN 2010 (4th Workshop on Dependable and Secure Nanocomputing, Chicago, IL, USA; 2010-06-28 - 2010-07-01; in: "WSDN - Full Program", IEEE Computer Socitey, (2010), ISBN: 9781424477289; 129 - 134.

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  38. Source: Faculty of Informatics

    W. Friesenbichler, T. Panhofer, A. Steininger:
    "Reliability Estimation and Experimental Results of a Self-Healing Asynchronous Circuit: A Case Study";
    Talk: NASA/ESA 2010 (Conference on Adaptive Hardware and Systems), Anaheim, CA, USA; 2010-06-15 - 2010-06-18; in: "NASA/ESA 2010 Proceedings", IEEE Computer Society, (2010), ISBN: 9781424458882; 97 - 104.

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  39. Source: Faculty of Informatics

    W. Friesenbichler, A. Steininger:
    "Soft Error Tolerant Asynchronous Circuits based on Dual Redundant Four State Logic";
    Talk: DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece; 2009-08-27 - 2009-08-29; in: "12th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - Architectures, Methods and Tools - DSD 2009", IEEE Computer Society, (2009), ISBN: 9780769537825; 100 - 107.

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  40. Source: Faculty of Informatics

    B. Fritz, V. S. Veeravalli, A. Steininger:
    "Reliable Gateway for Radiation Experiments on a VLSI Chip";
    Poster: Austrochip 2012, Graz, Austria; 2012-10-10; in: "Austrochip 2012", (2012), 65 - 70.

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  41. Source: Faculty of Informatics

    B. Fritz, V. S. Veeravalli, A. Steininger, V. Simek:
    "Setup for an Experimental Study of Radiation Effects in 65nm CMOS";
    Talk: 20th Euromicro Conference on Digital System Design, Wien; 2017-08-30 - 2017-09-01; in: "Proceedings of the 20th Euromicro Conference on Digital System Design", (2017), 329 - 336.

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  42. Source: Faculty of Informatics

    G. Fuchs, M Függer, U. Schmid, A. Steininger:
    "Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip";
    Talk: 11th EUROMICRO Conference on Digital System Design (DSD 2008), Parma, Italien; 2008-09-03 - 2008-09-05; in: "11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008.", IEEE, (2008), ISBN: 978-0-7695-3277-6; 242 - 249.

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  43. Source: Faculty of Informatics

    G. Fuchs, M Függer, A. Steininger:
    "On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme";
    Talk: ASYNC 2009 (International Symposium on Asynchronous Circuits and Systems), Chapel Hill, North Carolina; 2009-05-17 - 2009-05-20; in: "ASYNC 2009", IEEE Computer Society, (2009), ISSN: 1522-8681; 127 - 136.

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  44. Source: Faculty of Informatics

    G. Fuchs, M Függer, A. Steininger, F. Zangerl:
    "Analysis of Constraints in a Fault-Tolerant Distributed Clock Generation Scheme";
    Talk: 3rd International Workshop on Dependable Embedded Systems, Leeds; 2006-10-01; in: "WDES 2006 3rd Workshop on Dependable Embedded Systems", (2006), 22 - 27.

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  45. Source: Faculty of Informatics

    G. Fuchs, J. Grahsl, U. Schmid, A. Steininger, G. Kempf:
    "Threshold Modules -- Die Schlüsselelemente zur Verteilten Generierung eines Fehlertoleranten Taktes";
    Talk: Austrochip, Wien; 2006-10-11; in: "Austrochip Mikroelektroniktagung", (2006), 149 - 156.

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  46. Source: Faculty of Informatics

    M Függer, G. Fuchs, A. Steininger:
    "On the Stability and Robustness of Non-Synchronous Circuits with Timing Loops";
    Talk: WSDN 2009 (Workshop on Dependable and Secure Nanocomputing, Estoril, Lisbon, Portugal; 2009-06-29 - 2009-06-30; in: "WSDN 2009", Springer, (2009), ISBN: 9781424444212; 45 - 50.

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  47. Source: Faculty of Informatics

    M Függer, T. Handl, A. Steininger, J. Widder, C. Tögel:
    "An Efficient Test for a Transition Signalling based Up-/Down-Counter";
    Poster: Austrochip, Wien; 2006-10-11; in: "Austrochip Mikroelektroniktagung", (2006), 55 - 62.

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  48. Source: Faculty of Informatics

    R. Gallo, M. Delvai, W. Elmenreich, A. Steininger:
    "Revision and Verification of an Enhanced UART";
    Talk: IEEE International Workshop on Factory Communication Systems, Vienna, Austria; 2004-09-22 - 2004-09-24; in: "Proceedings of the 2004 IEEE International Workshop on Factory Communication Systems", IEEE, (2004), ISBN: 0-7803-8734-1; 315 - 318.

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  49. Source: Faculty of Informatics

    J. Grahsl, T. Handl, A. Steininger:
    "Exploring the Usefulness of the Gate-level Stuck-at Fault Model for Muller C-Elements";
    Poster: 20. GI/ITG/GMM Workshop Testmethoden und Vuverlässigkeit von Schaltungen und Systemen, Wien; 2008-02-24 - 2008-02-26; in: "20. Workshop Testmethoden und Vuverlässigkeit von Schaltungen und Systemen", (2008), 165 - 169.

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  50. Source: Faculty of Informatics

    J. Grahsl, T. Handl, A. Steininger, G. Kempf:
    "SAFE - A Scalable Environment for Automated Transistor Level Fault Effect Analysis";
    Talk: Austrochip, Graz; 2007-10-11; in: "Austrochip - Workshop on Microelectronics", (2007), 91 - 98.

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  51. Source: Faculty of Informatics

    T. Handl, A. Steininger:
    "Implementation of an FPGA-Based Hardware Fault Injector";
    Poster: Junior Scientist Conference, Wien; 2006-04-19 - 2006-04-21; in: "Junior Scientist Conference 2006", (2006), 23 - 24.

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  52. Source: Faculty of Informatics

    T. Handl, A. Steininger, G. Kempf:
    "Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit";
    Talk: International Design and Test Workshop (IDT), Kairo; 2007-12-16 - 2007-12-18; in: "Proceedings IDT'07 - The Second International Design and Test Workshop", (2007), 115 - 119.

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  53. Source: Faculty of Informatics

    T. Handl, A. Steininger, G. Kempf:
    "An Efficient Test Strategy for a Fault-Tolerant Clock Generator for Systems-on-Chip";
    Talk: 19. ITG/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Errlangen; 2007-03-11 - 2007-03-13; in: "19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (2007), 66 - 70.

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  54. Source: Faculty of Informatics

    M. Hofbauer, K. Schweiger, H. Zimmermann, U. Giesen, F. Langner, U. Schmid, A. Steininger:
    "Supply Voltage Dependent On-chip Single Event Transient Pulse Shape Measurements in 90 nm Bulk CMOS under Alpha Irradiation";
    Poster: 21st European Conference on Radiation and its Effects on Components and Systems (RADECS'12), Biarritz, FRANCE; 2012-09-24 - 2012-09-28; in: "Proceedings 21st European Conference on Radiation and its Effects on Components and Systems (RADECS'12)", (2012).

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  55. Source: Faculty of Informatics

    M. Horauer, E. Armengaud, A. Steininger:
    "Concepts and Tools for the Test of the Communication Sub-System of Time-Triggered Distributed Embedded Systems";
    Talk: International Conference on Design Engineering Technical Conferences & Computers and Information in Engineering (ASME), Las Vegas; 2007-09-04 - 2007-09-07; in: "ASME 2007 International Conference on Design Engineering Technical Conferences & Computers and Information in Engineering", (2007).

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  56. Source: Faculty of Informatics

    M. Horauer, F Rothensteiner, M Zauner, E. Armengaud, A. Steininger, H. Friedl, R. Pallierer:
    "An FPGA based SoC Design for Testing Embedded Automotive Communication Systems employing the FlexRay Protocol";
    Poster: Austrochip, Wien; 2004; in: "Austrochip 2004", TU-Wien, (2004), 119 - 123.

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  57. Source: Faculty of Informatics

    F. Huemer, J. Lechner, A. Steininger:
    "A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes";
    Poster: 2016 IEEE International Conference on Computer Design, Phoenix, Arizona, USA; 2016-10-03 - 2016-10-05; in: "Proceedings 2016 IEEE International Conference on Computer Design", (2016), ISBN: 978-1-5090-5142-7; 392 - 395.

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  58. Source: Faculty of Informatics

    F. Huemer, R. Najvirt, A. Steininger:
    "Identification and Confinement of Fault Sensitivity Windows in QDI Logic";
    Talk: 28th Austrian Workshop on Microelectronics, Wien; 2020-10-07; in: "Proceedings 28th Austrian Workshop on Microelectronics", (2020), 1 - 8.

  59. Source: Faculty of Informatics

    F. Huemer, M. Schütz, A. Steininger:
    "Revisiting Sorting Network based Completion Detection for 4 Phase Delay Insensitive Codes";
    Talk: Austrochip Workshop on Microelectronics, Wien; 2015-09-28; in: "Austrochip Workshop on Microelectronics", (2015), 6 pages.

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  60. Source: Faculty of Informatics

    F. Huemer, A. Steininger:
    "Sorting Network based Full Adders for QDI Circuits";
    Talk: 28th Austrian Workshop on Microelectronics, Wien; 2020-10-07; in: "Proceedings 28th Austrian Workshop on Microelectronics", (2020), 1 - 8.

  61. Source: Faculty of Informatics

    F. Huemer, A. Steininger:
    "Timing Domain Crossing using Muller Pipelines";
    Talk: 26th IEEE International Symposium on Asynchronous Circuits and Systems, Snowbird, Utah, USA; 2020-05-17 - 2020-05-20; in: "Proceedings 26th IEEE International Symposium on Asynchronous Circuits and Systems", Ieee Cs, (2020), ISSN: 2643-1483; 1 - 10.

  62. Source: Faculty of Informatics

    M. Jeitler, J. Lechner, A. Steininger:
    "Enhancing Pipelined Processor Architectures with Fast Autonomous Recovery of Transient Faults";
    Poster: DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria; 2010-04-14 - 2010-04-16; in: "13th IEEE International Symposium On Design And Diagnostics Of Electronic Cicruits And Systems", IEEE Computer Society, (2010), ISBN: 9781424466108; 233 - 236.

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  63. Source: Faculty of Informatics

    T. Kottke, A. Steininger:
    "A Dual Core Architecture with Error Containment";
    Talk: East-West Design & Test International Workshop(EWDTWī04), Yalta-Alushta, Crimea, Ukraine; 2004-09-23 - 2004-09-26; in: "East-West Design & Test International Workshop", (2004), ISBN: 966-659-088-3; 102 - 108.

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  64. Source: Faculty of Informatics

    T. Kottke, A. Steininger:
    "A Fail-Silent Reconfigurable Superscalar Processor";
    Talk: 13th Pacific Rim International Symposium on Dependable Computing (PRDC 07), Melbourne; 2007-12-17 - 2007-12-19; in: "13th Pacific Rim International Symposium on Dependable Computing (PRDC'07), Melbourne", (2007), 232 - 239.

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  65. Source: Faculty of Informatics

    T. Kottke, A. Steininger:
    "A Generic Dual-Core Architecture";
    Talk: 7th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2004), Stara Lesna, Slovakia; 2004-04-18 - 2004-04-21; in: "7th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2004)", (2004), ISBN: 80-969117-9-1; 159 - 166.

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  66. Source: Faculty of Informatics

    T. Kottke, A. Steininger:
    "A Reconfigurable Generic Dual-Core Architecture";
    Talk: IEEE International Conference on Dependable Systems and Networks, Philadelphia; 2006-06-25 - 2006-06-28; in: "Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN)", (2006), 45 - 54.

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  67. Source: Faculty of Informatics

    T. Kottke, A. Steininger:
    "Designoptimierung eines Prozessors mit Eigenfehlererkennung";
    Talk: 17. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen;, Inssbruck; 2005-02-27 - 2005-03-01; in: "16. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen;", (2005), 55 - 59.

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  68. Source: Faculty of Informatics

    T. Kottke, A. Steininger:
    "Vergleich zweier zwischen Sicherheit und Performanz rekonfigurierbarer Prozessorsysteme";
    Poster: 19. ITG/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Errlangen; 2007-03-11 - 2007-03-13; in: "19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (2007).

  69. Source: Faculty of Informatics

    J. Lechner, A. Steininger, F. Huemer:
    "Methods for Analysing and Improving the Fault Resilience of Delay-Insensitive Codes";
    Talk: 33rd IEEE International Conference on Computer Design, New York City, USA; 2015-10-19 - 2015-10-21; in: "33rd IEEE International Conference on Computer Design", (2015), 8 pages.

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  70. Source: Faculty of Informatics

    J. Maier, A. Steininger:
    "Efficient Metastability Characterization for Schmitt-Triggers";
    Talk: 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), Hirosaki, Japan; 2019-05-12 - 2019-05-15; in: "2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)", (2019), ISBN: 978-1-5386-4747-9; 124 - 133.

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  71. Source: Faculty of Informatics

    J. Maier, A. Steininger:
    "Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic";
    Talk: 17th Symposium on Design and Diagnosis of Electronic Circuits and Systems (DDECS 2014), Warschau, Polen; 2014-04-23 - 2014-04-25; in: "Design and Diagnostics of Electronic Circuits Systems (DDECS), 2014 IEEE 17th International Symposium on", (2014), 6 pages.

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  72. Source: Faculty of Informatics

    P. Milbredt, M. Glass, M. Lukasiewycz, A. Steininger, J. Teich:
    "Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach";
    Talk: Design, Automation & Test in Europe Conference & Exhibition (DATE 2012), Dresden, Germany; 2012-03-12 - 2012-03-16; in: "Design, Automation & Test in Europe Conference & Exhibition (DATE 2012) Proceedings", EDAA, (2012), ISBN: 978-3-9810801-8-6; 276 - 279.

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  73. Source: Faculty of Informatics

    P. Milbredt, M. Horauer, A. Steininger:
    "An Investigation of the Clique Problem in Flex Ray";
    Talk: SIESī2008 Third international symposium on industrial embedded systems, Montpellier - La Grande Motte, France; 2008-08-11 - 2008-08-13; in: "International Symposium on Industrial Embedded Systems, 2008.", (2008), ISBN: 978-1-4244-1995-1; 200 - 207.

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  74. Source: Faculty of Informatics

    P. Milbredt, A. Steininger, M. Horauer:
    "Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks";
    Talk: IEEE International Workshop on Electronic Design, Test and Applications, Hong-Kong; 2008-05-23 - 2008-05-25; in: "4th IEEE International Symposium on Electronic Design, Test and Applications, 2008. DELTA 2008.", (2008), ISBN: 978-0-7695-3110-6; 533 - 538.

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  75. Source: Faculty of Informatics

    R. Najvirt, S. Naqvi, A. Steininger:
    "Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs";
    Talk: 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2013), Santa Monica, CA; 2013-05-19 - 2013-05-22; in: "Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on", (2013), ISSN: 1522-8681; 9 pages.

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  76. Source: Faculty of Informatics

    R. Najvirt, T. Polzer, F. Beck, A. Steininger:
    "Containment of Metastable Voltages in FPGAs";
    Talk: 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Belgrad; 2015-04-22 - 2015-04-24; in: "18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", (2015), 6 pages.

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  77. Source: Faculty of Informatics

    R. Najvirt, T. Polzer, A. Steininger:
    "Measuring Metastability with Free-Running Clocks";
    Talk: 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, California; 2017-05-21 - 2017-05-24; in: "Proceedings 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017)", IEEE Computer Society, 10662 Los Vaqueros Circle (2017), ISBN: 978-1-5386-2749-5; Paper ID 37, 7 pages.

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  78. Source: Faculty of Informatics

    R. Najvirt, A. Steininger:
    "A Pausible Clock with Crystal Oscillator Accuracy";
    Talk: 22nd European Conference on Circuit Theory and Design, Trondheium, Norwegen; 2015-08-24 - 2015-08-26; in: "22nd European Conference on Circuit Theory and Design", (2015), Paper ID 67, 4 pages.

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  79. Source: Faculty of Informatics

    R. Najvirt, A. Steininger:
    "A Versatile and Reliable Glitch Filter for Clocks";
    Talk: 25th International Workshop on Power and Timing Modeling, Optimization and Simulation, Salvador, Brasilien; 2015-09-01 - 2015-09-04; in: "25th International Workshop on Power and Timing Modeling, Optimization and Simulation", (2015), 8 pages.

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  80. Source: Faculty of Informatics

    R. Najvirt, A. Steininger:
    "Equivalence of Clock Gating and Synchronization with Applicability to GALS Communication";
    Talk: 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, Isles Balears, Spain; 2014-09-29 - 2014-10-01; in: "Proceedings of the 24th International Workshop on Power and Timing Modeling, Optimization and Simulation", IEEE, (2014), ISBN: 978-1-4799-5412-4; Paper ID 29, 8 pages.

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  81. Source: Faculty of Informatics

    R. Najvirt, A. Steininger:
    "How to Synchronize a Pausible Clock to a Reference";
    Talk: 21st IEEE International Symposium on Asynchronous Circuits and Systems, Mountain View, CA; 2015-05-04 - 2015-05-06; in: "21st IEEE International Symposium on Asynchronous Circuits and Systems", (2015), 8 pages.

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  82. Source: Faculty of Informatics

    R. Najvirt, V. S. Veeravalli, A. Steininger:
    "Particle Strikes in C-Gates: Relevance of SET Shapes";
    Talk: 2nd Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale, Avignon; 2013-05-30 - 2013-05-31; in: "Proceedings of the MEDIAN Workshop 2013", (2013), 4 pages.

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  83. Source: Faculty of Informatics

    S. Naqvi, J. Lechner, A. Steininger:
    "Protection of Muller-Pipelines from Transient Faults";
    Talk: 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA; 2014-03-10 - 2014-03-12; in: "Proceedings 15th International Symposium & Exhibit on Quality Electronic Design", (2014), ISBN: 978-1-4799-3946-6; 9 pages.

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  84. Source: Faculty of Informatics

    S. Naqvi, R. Najvirt, A. Steininger:
    "A Multi-Credit Flow Control Scheme for Asynchronous NoCs";
    Talk: 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Karoly Vary, Czech Republic; 2013-04-08 - 2013-04-10; in: "Proc. 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems", (2013), 6 pages.

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  85. Source: Faculty of Informatics

    S. Naqvi, A. Steininger:
    "A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments";
    Talk: Design Automation &Test in Europe Conference and Exhibition 2014 (DATE 14), Dresden, Deutschland; 2014-03-24 - 2014-03-28; in: "Proceedings Design Automation &Test in Europe", (2014), ISBN: 978-3-9815370-2-4; 6 pages.

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  86. Source: Faculty of Informatics

    S. Naqvi, A. Steininger, J. Lechner:
    "An SET Tolerant Tree Arbiter Cell";
    Talk: 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2013), Santa Monica, CA; 2013-05-19 - 2013-05-22; in: "Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on", (2013), ISSN: 1522-8681; 9 pages.

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  87. Source: Faculty of Informatics

    S. Naqvi, V. S. Veeravalli, A. Steininger:
    "Protecting an Asynchronous NoC against Transient Channel Faults";
    Talk: DSD 2012 (Euromicro Conference on Digital System Design), Cesme, Izmir, Turkey; 2012-09-05 - 2012-09-08; in: "Proc. of 15th Euromicro Conference on Digital System Design", (2012), 8 pages.

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  88. Source: Faculty of Informatics

    R. Pallierer, M. Horauer, A. Steininger:
    "Monitoring and Fault Injection of X-by-Wire Communication Networks";
    Talk: Entwicklerforum Design & Elektronik: Drahtlose und drahtgebundene Netzwerke, Wien; 2004-02-03; in: "Entwicklerforum Design & Elektronik: Drahtlose und drahtgebundene Netzwerke", (2004).

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  89. Source: Faculty of Informatics

    A. Paverd, M. Völp, F. Brasser, M. Schunter, N. Asokan, A. Sadeghi, P. Esteves-Verissimo, A. Steininger, T. Holz:
    "Sustainable Security & Safety: Challenges andOpportunities";
    Talk: 4th International Workshop on Security and Dependability of Critical Embedded Real-Time Systems (CERTS 2019), Stuttgart; 2019-07-09; in: "Proceedings 4th International Workshop on Security and Dependability of Critical Embedded Real-Time Systems (CERTS 2019)", (2019), ISBN: 978-3-95977-119-1; 13 pages.

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  90. Source: Faculty of Informatics

    T. Polzer, T. Handl, A. Steininger:
    "A Metastability-Free Multi-synchronous Communication Scheme for SoCs";
    Talk: SSS 2009 (Symposium on Stabilization, Safety, and Security of Distributed Systems), Lyon, France; 2009-11-03 - 2009-11-06; in: "Stabilization, Safety, and Security of Distribiuted Systems", Springer, 5873/2009 (2009), ISBN: 978-3642051173; 578 - 592.

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  91. Source: Faculty of Informatics

    T. Polzer, F. Huemer, A. Steininger:
    "A Programmable Delay Line for Metastability Characterization in FPGAs";
    Talk: 24th Austrian Workshop on Microelectronics (Austrochip), Villach; 2016-10-19; in: "Proceedings 24th Austrian Workshop on Microelectronics", (2016), 6 pages.

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  92. Source: Faculty of Informatics

    T. Polzer, F. Huemer, A. Steininger:
    "Measuring Metastability Using a Time-to-Digital Converter";
    Talk: 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Dresden; 2017-04-19 - 2017-04-21; in: "Proceedings 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", IEEE Service Center, (2017), ISBN: 978-1-5386-0471-7; Paper ID 55, 6 pages.

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  93. Source: Faculty of Informatics

    T. Polzer, A. Steininger:
    "A General Approach for Comparing Metastable Behavior of Digital CMOS Gates";
    Talk: 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Kosice, Slovakia; 2016-04-20 - 2016-04-22; in: "Proc 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", (2016), ISBN: 978-1-5090-2467-4; 6 pages.

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  94. Source: Faculty of Informatics

    T. Polzer, A. Steininger:
    "An Approach for Efficient Metastability Characterization of FPGAs through the Designer";
    Talk: 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2013), Santa Monica, CA; 2013-05-19 - 2013-05-22; in: "19th IEEE International Symposium on Asynchronous Circuits and Systems", (2013), ISSN: 1522-8681; 9 pages.

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  95. Source: Faculty of Informatics

    T. Polzer, A. Steininger:
    "Digital Late-Transition Metastability Simulation Model";
    Talk: 16th Euromicro Conference on Digital System Design (DSD 2013), Santander; 2013-09-04 - 2013-09-06; in: "Proceedings of the 16th Euromicro Conference on Digital System Design", (2013), 8 pages.

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  96. Source: Faculty of Informatics

    T. Polzer, A. Steininger:
    "Enhanced Metastability Characterization based on AC Analysis";
    Talk: 18th Euromicro Conference on Digital System Design, Funchal, Portugal; 2015-08-26 - 2015-08-28; in: "18th Euromicro Conference on Digital System Design", (2015), 9 pages.

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  97. Source: Faculty of Informatics

    T. Polzer, A. Steininger:
    "Measuring the Distribution of Metastable Upsets over Time";
    Talk: 18th Euromicro Conference on Digital System Design, Funchal, Portugal; 2015-08-26 - 2015-08-28; in: "Measuring the Distribution of Metastable Upsets over Time", (2015), 8 pages.

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  98. Source: Faculty of Informatics

    T. Polzer, A. Steininger:
    "Metastability Characterization for Muller C-Elements";
    Talk: 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013), Karlsruhe; 2013-09-09 - 2013-09-11; in: "23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013)", (2013), 8 pages.

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  99. Source: Faculty of Informatics

    T. Polzer, A. Steininger:
    "SET Propagation in Micropipelines";
    Talk: 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013), Karlsruhe; 2013-09-09 - 2013-09-11; in: "23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013)", (2013), 8 pages.

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  100. Source: Faculty of Informatics

    T. Polzer, A. Steininger, J. Lechner:
    "Muller C-Element Metastability Containment";
    Talk: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2012, Newcastle upon Tyne; 2012-09-04 - 2012-09-06; in: "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation", Lecture Notes in Computer Science, 7606 (2013), ISBN: 978-3-642-36156-2; 103 - 112.

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  101. Source: Faculty of Informatics

    B. Rahbaran, M Függer, A. Steininger:
    "Embedded Real-Time-Tracer --An Approach with IDE";
    Talk: Workshop on Intelligent Solutions in Embedded Systems, Austria, Graz; 2004-06-25; in: "Proceedings of the Second Workshop on Intelligent Solutions in Embedded Systems", (2004), ISBN: 3-902463-00-7; 25 - 35.

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  102. Source: Faculty of Informatics

    B. Rahbaran, A. Steininger:
    "Real-time Fault Injection with Signal-Flip model by FIDYCO";
    Talk: IEEE International Conference on Dependable Systems and Networks, Florence, Italy; 2004-06-28 - 2004-07-01; in: "DSN 2004 Supplement", IEEE Computer Society, Supplemental (2004), 70 - 71.

  103. Source: Faculty of Informatics

    B. Rahbaran, A. Steininger, T. Handl:
    "Built-in Fault Injection in Hardware-- The FIDYCO Example";
    Talk: IEEE International Workshop on Electronic Design, Test and Applications, Perth, Australia; 2004-01-28 - 2004-01-30; in: "Second IEEE International Workshop on Electronic Design, Test and Applications", B. Rahbaran, A. Steininger (ed.); IEEE Computer Society Press, Delta 2004, Perth Australia (2004), ISBN: 0-7695-2081-2; 327 - 332.

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  104. Source: Faculty of Informatics

    T. Reinbacher, J. Brauer, M. Horauer, A. Steininger, S. Kowalewski:
    "Past time LTL runtime verification for microcontroller binary code";
    Talk: FMICS 2011, Trento; 2011-08-29 - 2011-08-30; in: "Formal Methods for Industrial Critical Systems", Springer Berlin / Heidelberg, (2011), ISBN: 978-3-642-24430-8; 37 - 51.

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  105. Source: Faculty of Informatics

    T. Reinbacher, J. Brauer, M. Horauer, A. Steininger, S. Kowalewski:
    "Test-Case Generation for Embedded Binary Code Using Abstract Interpretation";
    Talk: MEMICS 2010 (Mathematical and Engineering Methods in Computer Science), Mikulov, Czech Republic; 2010-10-22 - 2010-10-24; in: "MEMICS proceedings", (2010), 151 - 158.

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  106. Source: Faculty of Informatics

    T. Reinbacher, J. Brauer, D. Schachinger, A. Steininger, S. Kowalewski:
    "Automated test-trace inspection for microcontroller binary code";
    Talk: 2nd International Conference on Runtime Verification (RV 2011), San Francisco; 2011-09-27 - 2011-09-30; in: "Runtime Verification", (2011), 239 - 244.

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  107. Source: Faculty of Informatics

    T. Reinbacher, J. Geist, P. Moosbrugger, M. Horauer, A. Steininger:
    "Parallel Runtime Verification of Temporal Properties for Embedded Software";
    Talk: Mechatronics and Embedded Systems and Applications (MESA), 2012 IEEE/ASME International Conference on, Suzhou, China; 2012-07-08 - 2012-07-10; in: "Mechatronics and Embedded Systems and Applications (MESA), 2012 IEEE/ASME International Conference on", (2012), ISBN: 978-1-4673-2347-5; 224 - 231.

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  108. Source: Faculty of Informatics

    T. Reinbacher, M. Horauer, A. Steininger:
    "A Runtime Verification Unit for Microcontrollers";
    Talk: System, Software, SoC and Silicon Debug Conference (S4D), 2012, Vienna, Austria; 2012-09-19 - 2012-09-20; in: "System, Software, SoC and Silicon Debug Conference (S4D), 2012", (2012), ISSN: 2114-3684; 1 - 6.

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  109. Source: Faculty of Informatics

    T. Reinbacher, A. Steininger, T. Müller, M. Horauer, J. Brauer, S. Kowalewski:
    "Hardware support for efficient testing of embedded software";
    Talk: The 7th ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications, Washington; 2011-08-29 - 2011-08-31; in: "International Conference on Mechatronic and Embedded Systems and Applications", ASME, (2011).

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  110. Source: Faculty of Informatics

    S. Resch, A. Steininger, C. Scherrer:
    "Software Composability and Mixed Criticality for Triple Modular Redundant Architectures";
    Talk: SASSUR Workshop 2013, Toulouse; 2013-09-24; in: "Proceedings of the 2013 SASSUR Workshop", (2013), 4 pages.

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  111. Source: Faculty of Electrical Engineering and Information Technology

    C. Scherrer, A. Steininger et al.:
    "Automated Measurement of Computer Fault-Tolerance by Reproducible Fault Injection Experiments";
    Talk: Int. Symp. On Development in Digital Measuring an Instrumentation, Naples, Italy; 1998-09-01; in: "Proc. of the 10th Int. Symp. On Development in Digital Measuring an Instrumentation", (1998), 557 - 562.

  112. Source: Faculty of Informatics

    C. Scherrer, A. Steininger:
    "How does Resource Utilization Affect Fault Tolerance?";
    Talk: International Symp. on Defect and Fault Tolerance in VLSI-Systems, Mt. Fuji, Yamanashi, Japan; 2000-10-02 - 2000-10-06; in: "PROCEEDINGS", (2000), 418 - 425.

  113. Source: Faculty of Informatics

    C. Scherrer, A. Steininger:
    "Periodic Node Shutdown in a Fail-Silent Architecture - Risk or Rescue?";
    Poster: World Multiconference on Systemics, cybernetics and Informatics, Orlando, Florida, USA; 2000-07-14 - 2000-07-18; in: "PROCEEDINGS", (2000), 205 - 210.

  114. Source: Faculty of Electrical Engineering and Information Technology

    C. Scherrer, A. Steininger:
    "Periodic Node Shutdown in a Fail-Silent Architecture - Risk or Rescue?";
    Talk: World Multiconference on Systemics, Cybernetics and Informatics (SCI), Orlando, FL, USA; 2000-07-23 - 2000-07-26; in: "World Multiconference on Systemics, Cybernetics and Informatics", (2000), 312 - 317.

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  115. Source: Faculty of Electrical Engineering and Information Technology

    C. Scherrer, A. Steininger et al.:
    "VIRUS - ein Instrumentarium für Reproduzierbare Pin-Level Fehlerinjektion";
    Talk: ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Herrenberg, Deutschland; 1998-03-01; in: "Tagungsband ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (1998), ???.

  116. Source: Faculty of Informatics

    U. Schmid, A. Steininger, H. Veith:
    "Towards a Systematic Design of Fault-Tolerant Asynchronous Circuits";
    Poster: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf, München; 2007-03-26 - 2007-03-28; in: "Fachtagung Zuverlässigkeit und Entwurf", VDE Verlag, (2007), ISBN: 978-3-8007-3023-0; 173 - 174.

  117. Source: Faculty of Informatics

    M. Schütz, F. Huemer, A. Steininger:
    "A Practical Comparison of 2-Phase Delay Insensitve Communication Protocols";
    Talk: Austrochip Workshop on Microelectronics, Wien; 2015-09-28; in: "Austrochip Workshop on Microelectronics", (2015), 6 pages.

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  118. Source: Faculty of Electrical Engineering and Information Technology

    A. Steininger et al.:
    "A Prototype Implementation of a TTP/C Controller";
    Talk: Proc. SAE World Congress 1997, Detroit; 1997-02-01; in: "Proc. SAE World Congress 1997", (1997), ???.

  119. Source: Faculty of Electrical Engineering and Information Technology

    A. Steininger:
    "Built-in Self-Test von VLSI-Bausteinen";
    Talk: Informationstagung Mikroelektronik (ME), Wien; 1997-10-01; in: "Mikroelektronik Tagung ME97", Schriftenreihe des ÖVE Nr. 14/1997, (1997), 181 - 186.

  120. Source: Faculty of Informatics

    A. Steininger:
    "Embedded Systems im Auto - Ein Vorbild für die Bahn?";
    Talk: Tagung, TU-Wien, Prechtlsaal; 2004-03-11; in: "Intelligenz im Schienenverkehr: Sicherheitsstandarts und effiziente Kapatzitätsnutzung", (2004), #.

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  121. Source: Faculty of Informatics

    A. Steininger:
    "Error Containment in the Presence of Metastability";
    Talk: Dagstuhl Seminar 08371 : Fault-Tolerant Distributed Algorithms on VLSI Chips, Dagstuhl, Germany (invited); 2009-09-07 - 2009-09-10; in: "Fault-Tolerant Distributed Algorithms on VLSI Chips", Leibniz Zentrum Informatik, 08371 (2009), ISSN: 1862-4405; ?.

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  122. Source: Faculty of Electrical Engineering and Information Technology

    A. Steininger:
    "Evaluation of Computer Fault-Tolerance by Fault Injection - A Measurement Problem ?";
    Poster: Int. Symp. On Development in Digital Measuring an Instrumentation, Naples, Italy; 1998-09-01; in: "Proc. of the 10th Int. Symp. On Development in Digital Measuring an Instrumentation (ISDDMI)", (1998), 766 - 771.

  123. Source: Faculty of Electrical Engineering and Information Technology

    A. Steininger:
    "How Reproducible shoult Fault-Injection be ?";
    Poster: International Symposium on Fault Tolerant Computing (FTCS), München, Deutschland; 1998-06-01; in: "Digest of FastAbstracts 28th IInternational Symposium on Fault Tolerant Computing (FTCS-28)", (1998), 80 - 81.

  124. Source: Faculty of Electrical Engineering and Information Technology

    A. Steininger:
    "Selbstteststrategie für einen Echtzeit-Kommunikationscontroller";
    Talk: ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Herrenberg, Deutschland; 1998-03-01; in: "Tagungsband ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (1998), ???.

  125. Source: Faculty of Informatics

    A. Steininger, M Függer, U. Schmid, G. Fuchs:
    "Fault-Tolerant Algorithms on SoCs - A case study";
    Talk: IEEE International Conference on Dependable Systems and Networks, Philadelphia; 2006-06-25 - 2006-06-28; in: "Supplement Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN)", (2006), 190 - 191.

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  126. Source: Faculty of Informatics

    A. Steininger, T. Handl, G. Fuchs, F. Zangerl:
    "Testing the Hardware Implementation of a Distributed Clock Generation Algorithm for SoCs";
    Talk: East-West Design & Test International Workshop (EWDTW'06), Sochi (invited); 2006-09-15 - 2006-09-19; in: "East-West Design & Test International Workshop", (2006), 59 - 64.

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  127. Source: Faculty of Informatics

    A. Steininger, T. Kottke:
    "A Fail-Silent Memory for Automotive Applications";
    Talk: European Test Symposium, Ajaccio,Corsica,France; 2004-05-23 - 2004-05-26; in: "9th European Test Symposium", (2004), 253 - 258.

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  128. Source: Faculty of Informatics

    A. Steininger, T. Kottke:
    "Concurrent Checking eines Adressdecoders";
    Talk: 16. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Dresden, Germany; 2004-02-29 - 2004-03-02; in: "GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (2004), 25 - 29.

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  129. Source: Faculty of Informatics

    A. Steininger, T. Kottke:
    "Ein dynamisch rekonfigurierbarer superskalarer Prozessor mit den Modi Sicherheit und Performanz";
    Talk: 18. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Titisee; 2006-03-12 - 2006-03-14; in: "18. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (2006), 36 - 40.

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  130. Source: Faculty of Informatics

    A. Steininger, J. Maier, R. Najvirt:
    "The Metastable Behavior of a Schmitt-Trigger";
    Talk: 22nd IEEE International Symposium on Asynchronous Circuits and Systems, Porto Alegre -- Brazil; 2016-05-08 - 2016-05-11; in: "2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)", IEEE Computer Society Conference Publishing Services (CPS), (2016), ISBN: 978-1-4673-9007-1; 57 - 64.

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  131. Source: Faculty of Informatics

    A. Steininger, R. Najvirt, J. Maier:
    "Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior?";
    Talk: 2016 Euromicro Conference on Digital System Design (DSD), Limassol, Portugal; 2016-08-31 - 2016-09-02; in: "2016 Euromicro Conference on Digital System Design (DSD)", IEEE, (2016), ISBN: 978-1-5090-2817-7; 372 - 379.

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  132. Source: Faculty of Informatics

    A. Steininger, B. Rahbaran, T. Handl:
    "Built-in Fault Injectors - The Logical Continuation of BIST?";
    Talk: Workshop on Intelligent Solutions in Embedded Systems (WISES'03), Wien; 2003-06-27; in: "Proceeding of the First Workshop on Intelligent Solutions in Embedded Systems", (2003), 187 - 196.

  133. Source: Faculty of Informatics

    A. Steininger, C. Scherrer:
    "How To Tune the MTTF of a Fault-Tolerant System";
    Talk: International Symp. on Defect and Fault Tolerance in VLSI-Systems, San Francisco, California, USA; 2001-10-02 - 2001-10-06; in: "PROCEEDINGS", (2001), 251 - 256.

  134. Source: Faculty of Electrical Engineering and Information Technology

    A. Steininger, C. Scherrer:
    "On Finding an Optimal Combination of Error Detection Mechanisms Based on Results of Fault Injection Experiments";
    Talk: International Symposium on Fault Tolerant Computing (FTCS), Seattle, Washington; 1997-06-18; in: "Proc. of the 27th Annual Int. Symp. On Fault Tolerant Computing (FTCS-27)", (1997), 238 - 247.

  135. Source: Faculty of Electrical Engineering and Information Technology

    A. Steininger, C. Scherrer:
    "On the Necessity of On-Line BIST in Safety-Critical Applications - A Case Study";
    Talk: International Symposium on Fault Tolerant Computing (FTCS), Madison, WI, USA; 1999-06-01; in: "Proc.. of the 29th Annual International Symposium on Fault Tolerant Computing (FTCS-29)", (1999), 208 - 215.

  136. Source: Faculty of Informatics

    A. Steininger, M. Schwendinger:
    "A Systematic Approach to Clock Failure Detection";
    Talk: Austrochip Workshop on Microelectronics, Wien; 2019-10-24; in: "2019 Austrochip Workshop on Microelectronics (Austrochip)", (2019), ISBN: 978-1-7281-1953-3; 35 - 42.

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  137. Source: Faculty of Informatics

    A. Steininger, V. S. Veeravalli, D. Alexandrescu, E. Costenaro, L. Anghel:
    "Exploring the State Dependent SET Sensitivity of Asynchronous Logic - The Muller-Pipeline Example";
    Talk: 2014 32nd IEEE International Conference on Computer Design (ICCD), Seoul, Korea; 2014-10-19 - 2014-10-22; in: "Proceedings of the 2014 32nd IEEE International Conference on Computer Design (ICCD)", IEEE, (2014), ISBN: 978-1-4799-6492-5; Paper ID 69, 7 pages.

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  138. Source: Faculty of Informatics

    A. Steininger, J. Vilanek:
    "Using Offline and Online BIST to Improve System Dependability - The TTPC-C Example";
    Talk: IEEE INTERNATIONAL CONFERENCE ON COMPUTER Design: VLSI in Computers & Processors, Freiburg, Germany; 2002-09-16 - 2002-09-18; in: "Computer Design: VLSI in Computers & Processors", (2002), 277 - 280.

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  139. Source: Faculty of Informatics

    Z. Tabassam, P. Behal, R. Najvirt, A. Steininger:
    "Input/Output-Interlocking for Fault Mitigation in QDI Pipelines";
    Talk: 29th Austrian Workshop on Microelectronics, Linz; 2021-10-14; in: "Proceedings 29th Austrian Workshop on Microelectronics", (2021), ISBN: 978-1-6654-3661-8; 4 pages.

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  140. Source: Faculty of Informatics

    P Tummeltshammer, A. Steininger:
    "On the Risk of Fault Coupling over the Chip Substrate";
    Talk: DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece; 2009-08-27 - 2009-08-29; in: "12th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - Architectures, Methods and Tools - DSD2009", IEEE Computer Society, (2009), ISBN: 9780769537825; 325 - 332.

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  141. Source: Faculty of Informatics

    P Tummeltshammer, A. Steininger:
    "On the Role of the Power Supply as an Entry for Common Cause Faults - An Experimental Analysis";
    Talk: DDECS 2009 (Design and Diagnostics of Electronic Circuits and Systems), Liberec, Czech Republic; 2009-04-15 - 2009-04-17; in: "2009 IEEE Design and Diagnostics of Electronic Circuits and Systems", IEEE, 00 (2009), ISBN: 9781424433414; 152 - 157.

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  142. Source: Faculty of Informatics

    P Tummeltshammer, A. Steininger:
    "Power Supply Induced Common Cause Faults - Experimental Assessment of Potential Countermeasures";
    Talk: DSN 2009 (International Conference on Dependable Systems and Networks), Estoril, Portugal; 2009-06-29 - 2009-07-02; in: "DSN 2009 - Full Program", Springer, (2009), ISBN: 9781424444212; 449 - 457.

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  143. Source: Faculty of Informatics

    P Tummeltshammer, A. Steininger:
    "Time-Multiplexed Multiple Constant Multiplication";
    Talk: Junior Scientist Conference, Wien; 2006-04-19 - 2006-04-21; in: "Junior Scientist Conference 2006", (2006), 77 - 78.

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  144. Source: Faculty of Informatics

    V. S. Veeravalli, A. Steininger:
    "Architecture for Monitoring SET Propagation in 16-bit Sklansky Adder";
    Poster: 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA; 2014-03-10 - 2014-03-12; in: "Proceedings 15th International Symposium & Exhibit on Quality Electronic Design", (2014), ISBN: 978-1-4799-3946-6; 8 pages.

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  145. Source: Faculty of Informatics

    V. S. Veeravalli, A. Steininger:
    "Can we trust SET Injection Models?";
    Talk: MEDIAN Finale Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale, Tallinn, Estonia; 2015-11-10 - 2015-11-11; in: "MEDIAN Finale Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale", (2015), 6 pages.

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  146. Source: Faculty of Informatics

    V. S. Veeravalli, A. Steininger:
    "Design and Physical Implementation of a Target ASIC for SET Experiments";
    Poster: 2016 Euromicro Conference on Digital System Design (DSD), Limassol, Portugal; 2016-08-31 - 2016-09-02; in: "Proc. 2016 Euromicro Conference on Digital System Design (DSD)", IEEE, (2016), ISBN: 978-1-5090-2817-7; 694 - 697.

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  147. Source: Faculty of Informatics

    V. S. Veeravalli, A. Steininger:
    "Diagnosis of SET Propagation in Combinational Logic under Dynamic Operation";
    Poster: 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10), Stanford University, USA; 2014-04-01 - 2014-04-02; in: "Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10)", (2014), 6 pages.

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  148. Source: Faculty of Informatics

    V. S. Veeravalli, A. Steininger:
    "Efficient Radiation-Hardening of a Muller C-Element";
    Talk: 2012 Single Event Effects Symposium (SEE 2012), San Diego, USA; 2012-04-03 - 2012-04-05; in: "2012 Single Event Effects Symposium", (2012).

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  149. Source: Faculty of Informatics

    V. S. Veeravalli, A. Steininger:
    "LFSR Implementation Using C-Elements";
    Talk: MEMICS 2012, Znjomo, Czechia; 2012-10-25 - 2012-10-28; in: "MEMICS 2012", (2012), 73 - 83.

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  150. Source: Faculty of Informatics

    V. S. Veeravalli, A. Steininger:
    "Long Term On-Chip Monitoring of SET Pulsewidths in a Fully Digital ASIC";
    Talk: 22nd Austrian Workshop on Microelectronics, Graz; 2014-10-09; in: "Proceedings of the 22nd Austrian Workshop on Micorelectronics", IEEE, (2014), ISBN: 978-1-4799-7243-2; Paper ID 24, 6 pages.

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