author = {O'Sullivan, B. J. and Ritzenthaler, Romain and Rzepa, Gerhard and Wu, Zhicheng and Litta, Eugenio Dentoni and Richard, Olivier and Conard, Thierry and Machkaoutsan, Vladimir and Fazan, Pierre and Kim, Cheolgyu and Franco, J. and Kaczer, Ben and Grasser, Tibor and Spessot, Alessio and Linten, D and Horiguchi, N.},
    title = {{Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-{$\kappa$}/Metal Gate Devices}},
    booktitle = {{P}roceedings of the {I}{E}{E}{E} {I}nternational {R}eliability {P}hysics {S}ymposium ({I}{R}{P}{S})},
    year = {2019},
    pages = {1--8},
    url = {http://www.iue.tuwien.ac.at/pdf/ib_2019/CP2019_OSullivan_1.pdf},
    isbn = {978-1-5386-9504-3},
    doi = {10.1109/IRPS.2019.8720598},
    note = {talk: {I}{E}{E}{E} {I}nternational {R}eliability {P}hysics {S}ymposium ({I}{R}{P}{S}), {M}onterey, {C}{A}, {U}{S}{A}; 2019-03-31 -- 2019-04-04}

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