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Publikationsliste für Angehörige von
E182 - Institut für Technische Informatik
als Autorinnen / Autoren bzw. wesentlich beteiligte Personen

1186 Datensätze (1997 - 2017)

Die Publikationen der Fakultät für Informatik sind erst ab dem Jahr 2002 vollzählig in der Publikationsdatenbank enthalten. Publikationen aus den Jahren vor 2002 können, müssen aber nicht in der Datenbank vorhanden sein.


Bücher und Buch-Herausgaben


  1. Autor/innen: Ezio Bartocci, E182 - 1; Luca Bortolussi, Univ. of Trieste

    E. Bartocci, L. Bortolussi (Hrg.):
    "Proceedings First International Workshop on Hybrid Systems and Biology";
    Electronic Proceedings in Theoretical Computer Science, 2012, ISSN: 2075-2180.

  2. Autor/innen: Ezio Bartocci, E182 - 1; Pietro Lio; Nicola Paoletti

    E. Bartocci, P. Lio, N. Paoletti (Hrg.):
    "Computational Methods in Systems Biology - 14th International Conference, CMSB 2016, Cambridge, UK, September 21-23, 2016, Proceedings";
    Springer International Publishing, Switzerland, 2016, ISBN: 978-3-319-45176-3; 356 S.

  3. Autor/innen: Ezio Bartocci, E182 - 1; Rupak Majumdar

    E. Bartocci, R. Majumdar (Hrg.):
    "Runtime Verification - 6th International Conference, {RV} 2015 Vienna, Austria, September 22-25, 2015. Proceedings";
    Springer International Publishing, Switzerland, 2015, ISBN: 978-3-319-23819-7; 432 S.

  4. Autor/innen: Ezio Bartocci, E182 - 1; C.R. Ramakrishnan

    E. Bartocci, C. Ramakrishnan (Hrg.):
    "Model Checking Software - 20th International Symposium, SPIN 2013, Stony Brook, NY, USA, July 8-9, 2013, Proceedings";
    Springer-Verlag Berlin Heidelberg, Berlin Heidelberg, 2013, ISBN: 978-3-642-39175-0; 377 S.

  5. Autor/innen: Roderick Bloem; Swen Jacobs, TU Graz; Ayrat Khalimov, TU Graz; Igor Konnov, E184 - 4; Sasha Rubin, E184 - 4; Helmut Veith, E184 - 4; Josef Widder, E182 - 2

    R. Bloem, S. Jacobs, A. Khalimov, I. Konnov, S. Rubin, V. Veith, J. Widder:
    "Decidability of Parameterized Verification";
    Morgan & Claypool Publishers, San Rafael, CA, USA, 2015, ISBN: 9781627057431; 170 S.

  6. Autor/innen: Andrea Bondavalli, UNIFI; Sara Bouchenak; Hermann Kopetz, E182 - 1
    Andere beteiligte Personen: David Hutchison, Lancaster University; Takeo Kanade, Carnegie Mellon Univ; Josef Kittler; Jon M. Kleinberg; Friedemann Mattern; John C. Mitchell; Moni Naor; C. Pandu Rangan; Bernhard Steffen; Demetri Terzopoulos; Doug Tygar; Gerhard Weikum

    A. Bondavalli, S. Bouchenak, H. Kopetz:
    "Cyber-Physical Systems of Systems, Foundations - A Conceptual Model and Some Derivations: The AMADEOS Legacy";
    in Buchreihe "Lecture Notes in Computer Science", Buchreihen-Herausgeber: D. Hutchison, T. Kanade, J. Kittler, J. Kleinberg, F. Mattern, J. Mitchell, M. Naor, C. Pandu Rangan, B. Steffen, D. Terzopoulos, D. Tygar, G. Weikum et al.; Springer International Publishing, 2016, ISBN: 978-3-319-47589-9, 257 S.

    Zusätzliche Informationen

  7. Autor/innen: Bernadette Charron-Bost; Shlomi Dolev; Jo Ebergen; Ulrich Schmid, E182 - 2
    Andere beteiligte Personen: Bernadette Charron-Bost; Shlomi Dolev; Ulrich Schmid, E182 - 2

    B. Charron-Bost, S. Dolev, J. Ebergen, U. Schmid:
    "Fault-Tolerant Distributed Algorithms on VLSI Chips";
    in Buchreihe "Dagstuhl Seminar Proceedings", Buchreihen-Herausgeber: B. Charron-Bost, S. Dolev, U. Schmid; herausgegeben von: Leibniz Zentrum Informatik; Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany, 2009, ISSN: 1862-4405.

    Zusätzliche Informationen

  8. Autor/in: Wilfried Elmenreich, E182 - 1

    W. Elmenreich (Hrg.):
    "Proceedings of the First Workshop on Intelligent Solutions in Embedded Systems";
    TU Wien, Vienna, Austria, 2003, 207 S.

    Zusätzliche Informationen

  9. Autor/in: Wilfried Elmenreich, E182 - 1

    W. Elmenreich et al. (Hrg.):
    "Systemnahes Programmieren - C Programmierung unter Unix und Linux";
    UBooks Verlag, Augsburg, 2002, ISBN: 3-935789-88-1; 290 S.

    Zusätzliche Informationen

  10. Autor/innen: Wilfried Elmenreich, E182 - 1; Wolfgang Haidinger, E182 - 1; J. A. Tenreiro Machado, ISEP, Porto

    W. Elmenreich, W. Haidinger, J.A.T. Machado (Hrg.):
    "Proceedings of the 2nd IEEE International Conference on Computational Cybernetics ";
    TU Wien, Wien, 2004, ISBN: 3-902463-01-5; 461 S.

  11. Autor/innen: Wilfried Elmenreich, E182 - 1; Hans Kaiser, E104

    W. Elmenreich, H. Kaiser (Hrg.):
    "Proceedings of the Junior Scientist Conference 2006";
    TU Wien, Wien, Österreich, 2006, ISBN: 3-902463-05-8; 359 S.

  12. Autor/innen: Wilfried Elmenreich, E182 - 1; J. A. Tenreiro Machado, ISEP, Porto; Imre J. Rudas

    W. Elmenreich, J.A.T. Machado, I. J. Rudas (Hrg.):
    "Intelligent Systems at the Service of Mankind, Volume I";
    UBooks Verlag, Augsburg, Deutschland, 2003, ISBN: 3-935798-25-3; 444 S.

  13. Autor/innen: Wilfried Elmenreich, E182 - 1; J. A. Tenreiro Machado, ISEP, Porto; Imre J. Rudas

    W. Elmenreich, J.A.T. Machado, I. J. Rudas (Hrg.):
    "Intelligent Systems at the Service of Mankind, Volume II";
    UBooks Verlag, Augsburg, Deutschland, 2005, ISBN: 3-86608-052-2; 478 S.

  14. Autor/innen: Wilfried Elmenreich, E182 - 1; Gregor Novak, E384; Ralf Seepold, Univ. de Madrid

    W. Elmenreich, G. Novak, R. Seepold (Hrg.):
    "Proceedings of the Fourth Workshop on Intelligent Solutions in Embedded Systems";
    TU Wien, Wien, Österreich, 2006, ISBN: 3-902463-06-6; 201 S.

  15. Autor/innen: Hans Kaiser, E104; Raimund Kirner, E182 - 1

    H. Kaiser, R. Kirner (Hrg.):
    "Junior Scientist Conference 2008, Proceedings";
    TU Wien, 2008.

  16. Autor/in: Raimund Kirner, E182 - 1

    R. Kirner:
    "Compiler Support for Timing Analysis of Optimized Code - Precise Timing Analysis of Machine Code with Convenient Annotation of Source Code";
    VDM - Verlag Dr. Müller, 2008, ISBN: 978-3836468831; 224 S.

    Zusätzliche Informationen

  17. Autor/in: Raimund Kirner, E182 - 1

    R. Kirner (Hrg.):
    "Worst-Case Execution Time Analysis (Proceedings of the 8th International Workshop WCET 2008)";
    Österreichische Computer Gesellschaft, Wien, 2008, ISBN: 978-3-85403-237-3; 173 S.

    Zusätzliche Informationen

  18. Autor/innen: Roman Obermaisser, Universität Siegen; Yunmook Nah; Peter Puschner, E182 - 1; Franz J. Rammig

    R. Obermaisser, Y. Nah, P. Puschner, F. Rammig (Hrg.):
    "Software Technologies for Embedded Systems and Ubiquitous Systems";
    Springer LNCS 4761, 2007, ISBN: 978-3-540-75663-7; 563 S.

  19. Autor/in: Peter Puschner, E182 - 1

    P. Puschner (Hrg.):
    "Proceedings of the 16th Euromicro Conference on Real-Time Systems";
    IEEE Computer Society Press, Piscataway, NJ, USA, 2004, ISBN: 0-7695-2176-2; 282 S.

  20. Autor/innen: Peter Puschner, E182 - 1; Tatsuo Nakajima; Arif Ghafoor

    P. Puschner, T. Nakajima, A. Ghafoor (Hrg.):
    "Proceedings of the Sixth International Symposium on Object-Oriented Real-Time Distributed Computing";
    IEEE Computer Society Press, Piscataway, NJ, USA, 2003, ISBN: 0-7695-1928-8; 302 S.

  21. Autor/innen: Bernhard Rinner; Wilfried Elmenreich, E182 - 1

    B. Rinner, W. Elmenreich (Hrg.):
    "Proceedings of the Second Workshop on Intelligent Solutions in Embedded Systems";
    Technische Universität Graz, Graz, Österreich, 2004, ISBN: 3-902463-00-7; 203 S.

  22. Autor/in: Martin Schoeberl, E182 - 1

    M. Schoeberl (Hrg.):
    "JOP Reference Handbook";
    CreateSpace, 2009, ISBN: 978-1438239699; 362 S.

    Zusätzliche Informationen

  23. Autor/in: Martin Schoeberl, E182 - 1

    M. Schoeberl:
    "JOP: A Java Optimized Processor for Embedded Real-Time Systems";
    VDM - Verlag Dr. Müller, 2008, ISBN: 978-3-8364-8086-4; 256 S.

    Zusätzliche Informationen


Zeitschriftenartikel


  1. Autor/innen: Daniel Albeseder, E182 - 2; Matthias Függer, E182 - 2; Felix Breitenecker, E101 - 6; Thomas Löscher, E101 - 6; Shabnam Michele Tauböck, E101 - 6

    D. Albeseder, M Függer, F. Breitenecker, T. Löscher, S. Tauböck:
    "Small PC-Network Simulation -- A Comprehensive Performance Case Study";
    Simulation News Europe, 44/45 (2005), S. 26 - 32.

  2. Autor/innen: Roberta Alfieri; Ezio Bartocci, E182 - 1; Emanuela Merelli; Luciano Milanesi

    R. Alfieri, E. Bartocci, E. Merelli, L. Milanesi:
    "Modeling the cell cycle: From deterministic models to hybrid systems";
    Biosystems, 105 (2011), 1; S. 34 - 40.

    Zusätzliche Informationen

  3. Autor/innen: Islam Ariful, Stony Brook U; Abhishek Murthy, Stony Brook U; Ezio Bartocci, E182 - 1; Elizabeth Cherry, Rochester Inst.; Flavio H. Fenton, Cornell U.; James Glimm, Stony Brook U; Scott A. Smolka, Stony Brook U; Radu Grosu, E182 - 1

    I. Ariful, A. Murthy, E. Bartocci, E. Cherry, F. Fenton, J. Glimm, S. Smolka, R. Grosu:
    "Model-Order Reduction of Ion Channel Dynamics Using Approximate Bisimulation";
    Theoretical Computer Science, 599 (2015), S. 34 - 46.

    Zusätzliche Informationen

  4. Autor/innen: Eric Armengaud, E182 - 2; Andreas Steininger, E182 - 2; Martin Horauer, E384

    E. Armengaud, A. Steininger, M. Horauer:
    "Towards a Systematic Test for Embedded Automotive Communication Systems";
    IEEE Transactions on Industrial Informatics, 4 (2008), 3; S. 145 - 208.

    Zusätzliche Informationen

  5. Autor/innen: Ezio Bartocci, E182 - 1; Ebru Aydin Gol, Boston University; Iman Haghighi; Calin Belta, Boston University

    E. Bartocci, E. Aydin Gol, I. Haghighi, C. Belta:
    "A Formal Methods Approach to Pattern Recognition and Synthesis in Reaction Diffusion Networks";
    IEEE Transactions on Control of Network Systems, PP (2016), 99; S. 1 - 12.

    Zusätzliche Informationen

  6. Autor/innen: Ezio Bartocci, E182 - 1; Luca Bortolussi, Univ. of Trieste; Tomas Brazdil; Dimitrios Milos; Guido Sanguinetti

    E. Bartocci, L. Bortolussi, T. Brazdil, D. Milos, G. Sanguinetti:
    "Policy learning in Continuous-Time Markov Decision Processes using Gaussian Processes";
    Performance Evaluation, 116 (2017), S. 84 - 100.

  7. Autor/innen: Ezio Bartocci, E182 - 1; Luca Bortolussi, Univ. of Trieste; Laura Nenzi, IMT Lucca; Guido Sanguinetti

    E. Bartocci, L. Bortolussi, L. Nenzi, G. Sanguinetti:
    "System Design of Stochastic Models using Robustness of Temporal Properties";
    Theoretical Computer Science, 587 (2015), S. 3 - 25.

    Zusätzliche Informationen

  8. Autor/innen: Ezio Bartocci, E182 - 1; Diletta Cacciagrano, Camerino; Maria Rita Di Berardini, Camerino; Emanuela Merelli; Leonardo Vito, Camerino

    E. Bartocci, D. Cacciagrano, M. Di Berardini, E. Merelli, L. Vito:
    "UBioLab: a web-LABoratory for Ubiquitous in-silico experiments";
    Journal of Integrative Bioinformatics, 9 (2012), 1; S. 1 - 20.

    Zusätzliche Informationen

  9. Autor/in: Ezio Bartocci, E182 - 1

    E. Bartocci et al.:
    "Teaching cardiac electrophysiology modeling to undergraduate students: Laboratory exercises and GPU programming for the study of arrhythmias and spiral wave dynamics";
    Advances in Physiology Education, 35 (2011), 4; S. 427 - 437.

  10. Autor/innen: Ezio Bartocci, E182 - 1; Oliver Höftberger, E182 - 1; Radu Grosu, E182 - 1

    E. Bartocci, O. Höftberger, R. Grosu:
    "Cyber-Physical Systems: Theoretical and Practical Challenges";
    ERCIM NEWS (eingeladen), 2014 (2014), 97; S. 8 - 9.

  11. Autor/innen: Ezio Bartocci, E182 - 1; Pietro Lio

    E. Bartocci, P. Lio:
    "Computational modeling, formal analysis and tools for systems biology";
    PLoS Computational Biology, 12 (2016), 1; S. 1 - 22.

    Zusätzliche Informationen

  12. Autor/innen: Ezio Bartocci, E182 - 1; Pietro Lio; Emanuela Merelli; Nicola Paoletti

    E. Bartocci, P. Lio, E. Merelli, N. Paoletti:
    "Multiple Verification in Complex Biological Systems: The Bone Remodelling Case Study";
    Transactions on Computational Systems Biology, XIV (2012), S. 53 - 76.

    Zusätzliche Informationen

  13. Autor/innen: Martin Biely, EPFL; Peter Robinson; Ulrich Schmid, E182 - 2

    M. Biely, P. Robinson, U. Schmid:
    "The Generalized Loneliness Detector and Weak System Models for k-Set Agreement";
    IEEE Transactions on Parallel and Distributed Systems, 25 (2014), 4; S. 1078 - 1088.

    Zusätzliche Informationen

  14. Autor/innen: Martin Biely, E182 - 2; Ulrich Schmid, E182 - 2; Bettina Weiss, E182 - 2

    M. Biely, U. Schmid, B. Weiss:
    "Synchronous consensus under hybrid process and link failures";
    Theoretical Computer Science, 412 (2011), 40; S. 5602 - 5630.

    Zusätzliche Informationen

  15. Autor/innen: Roderick Bloem; Swen Jacobs, TU Graz; Ayrat Khalimov, TU Graz; Igor Konnov, E184 - 4; Sasha Rubin; Helmut Veith, E184 - 4; Josef Widder, E182 - 2

    R. Bloem, S. Jacobs, A. Khalimov, I. Konnov, S. Rubin, V. Veith, J. Widder:
    "Decidability of Parameterized Verification";
    ACM SIGACT News, 47 (2016), 2; S. 53 - 64.

    Zusätzliche Informationen

  16. Autor/innen: Bernadette Charron-Bost; Matthias Függer, E182 - 2; Jennifer Welch, Texas A&M Univer; Josef Widder, E184 - 4

    B. Charron-Bost, M Függer, L. Welch, J. Widder:
    "Time Complexity of Link Reversal Routing";
    ACM Transactions on Algorithms, 11 (2015), 3; S. 1 - 39.

    Zusätzliche Informationen

  17. Autor/innen: Bernadette Charron-Bost; Martin Hutle, E182 - 2; Josef Widder, E182 - 2

    B. Charron-Bost, M. Hutle, J. Widder:
    "In search of lost time";
    Information Processing Letters, 110 (2010), 21; S. 928 - 933.

    Zusätzliche Informationen

  18. Autor/innen: Kuan-Hsun Chen, TUD; Jian-Jia Chen, TUD; Florian Kriebel, E182 - 2; Semeen Rehman, TUD; Muhammad Shafique, E182 - 2; Jörg Henkel, KIT

    K. Chen, J. Chen, F. Kriebel, S. Rehman, M. Shafique, J. Henkel:
    "Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity";
    IEEE Transactions on Computers, 65 (2016), 11; S. 3441 - 3454.

    Zusätzliche Informationen

  19. Autor/innen: Martin Delvai, E182 - 2; Ulrike Eisenmann; Wilfried Elmenreich, E182 - 1

    M. Delvai, U. Eisenmann, W. Elmenreich:
    "A Generic Architecture for Integrated Smart Transducers";
    Lecture Notes in Computer Science, 2778 (2003), S. 733 - 744.

    Zusätzliche Informationen

  20. Autor/innen: Danny Dolev; Matthias Függer, E182 - 2; Christoph Lenzen; Martin Perner, E182 - 2; Ulrich Schmid, E182 - 2

    D. Dolev, M Függer, C. Lenzen, M. Perner, U. Schmid:
    "HEX: Scaling Honeycombs is Easier than Scaling Clock Trees";
    Journal of Computer and System Sciences, 82 (2016), 5; S. 929 - 956.

    Zusätzliche Informationen

  21. Autor/innen: Danny Dolev; Matthias Függer, E182 - 2; Christoph Lenzen; Ulrich Schmid, E182 - 2; Andreas Steininger, E182 - 2

    D. Dolev, M Függer, C. Lenzen, U. Schmid, A. Steininger:
    "Fault-tolerant Distributed Systems in Hardware";
    Bulletin of the EATCS, 2 (2015), 116; 43 S.

  22. Autor/innen: Danny Dolev; Matthias Függer, E182 - 2; Markus Posch, E182 - 2; Ulrich Schmid, E182 - 2; Andreas Steininger, E182 - 2; Christoph Lenzen

    D. Dolev, M Függer, M. Posch, U. Schmid, A. Steininger, C. Lenzen:
    "Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip";
    Journal of Computer and System Sciences, 80 (2014), 4; S. 860 - 900.

    Zusätzliche Informationen

  23. Autor/innen: Danny Dolev; Matthias Függer, E182 - 2; Ulrich Schmid, E182 - 2; Christoph Lenzen

    D. Dolev, M Függer, U. Schmid, C. Lenzen:
    "Fault-tolerant Algorithms for Tick-generation in Asynchronous Logic: Robust Pulse Generation";
    Journal of the ACM, 61 (2014), 5; S. 1 - 74.

  24. Autor/innen: Christian El Salloum, E182 - 1; Martin Elshuber, E182 - 1; Oliver Höftberger, E182 - 1; Haris Isakovic, E182 - 1; Armin Wasicek, E182 - 1

    C. El Salloum, M. Elshuber, O. Höftberger, H. Isakovic, A. Wasicek:
    "The ACROSS MPSoC - A new generation of multi-core processors designed for safety-critical embedded systems";
    Microprocessors and Microsystems, 37 (2013), 8, Part C; S. 1020 - 1032.

    Zusätzliche Informationen

  25. Autor/in: Wilfried Elmenreich, E182 - 1

    W. Elmenreich:
    "A Review on System Architectures for Sensor Fusion Applications";
    Lecture Notes in Computer Science, 4761 (2007), S. 547 - 559.

    Zusätzliche Informationen

  26. Autor/in: Wilfried Elmenreich, E182 - 1

    W. Elmenreich:
    "Fusion of Continuous-valued Sensor Measurements using Confidence-weighted Averaging";
    Journal of Vibration and Control, 13 (2007), 9-10; S. 1303 - 1312.

    Zusätzliche Informationen

  27. Autor/in: Wilfried Elmenreich, E182 - 1

    W. Elmenreich:
    "Kostengünstig vernetzen mit TTP/A";
    Markt & Technik, 38 (2000), S. 42 - 44.

    Zusätzliche Informationen

  28. Autor/in: Wilfried Elmenreich, E182 - 1

    W. Elmenreich:
    "Time-Triggered Smart Transducer Networks";
    IEEE Transactions on Industrial Informatics, 2 (2006), 3; S. 192 - 199.

  29. Autor/innen: Wilfried Elmenreich, E182 - 1; Wolfgang Haidinger, E182 - 1; Hermann Kopetz, E182 - 1; Thomas Losert, E182 - 1; Roman Obermaisser, Universität Siegen; Harald Paulitsch, E182 - 1; Philipp Peti, E182 - 1

    W. Elmenreich, W. Haidinger, H. Kopetz, T. Losert, R. Obermaisser, H. Paulitsch, P. Peti:
    "A Standard for Real-time Smart Transducer Interface";
    Computer Standards & Interfaces, 28 (2006), 6; S. 613 - 624.

  30. Autor/innen: Martin Elshuber, E182 - 1; Roman Obermaisser, Universität Siegen

    M. Elshuber, R. Obermaisser:
    "Dependable and predictable time-triggered Ethernet networks with COTS components";
    Journal of Systems Architecture, Volume 59, Issue 9 (2013), S. 667 - 690.

    Zusätzliche Informationen

  31. Autor/innen: Lukas Esterle, E182 - 1; Radu Grosu, E182 - 1

    L. Esterle, R. Grosu:
    "Cyber-physical systems: challenge of the 21st century";
    Elektrotechnik und Informationstechnik (eingeladen), 133 (2016), 7; S. 299 - 303.

    Zusätzliche Informationen

  32. Autor/in: Markus Ferringer, E182 - 2

    M. Ferringer:
    "On Self-Timed Circuits in Real-Time Systems";
    International Journal of Reconfigurable Computing, 2011 (2011), 972375.

    Zusätzliche Informationen

  33. Autor/innen: Matthias Függer, E182 - 2; Alexander Kößler, E182 - 2; Thomas Nowak; Ulrich Schmid, E182 - 2; Martin Zeiner, E182 - 2

    M Függer, A. Kößler, T. Nowak, U. Schmid, M. Zeiner:
    "The effect of forgetting on the performance of a synchronizer";
    Performance Evaluation, 93 (2015), S. 1 - 16.

    Zusätzliche Informationen

  34. Autor/innen: Matthias Függer, E182 - 2; Thomas Nowak; Ulrich Schmid, E182 - 2

    M Függer, T. Nowak, U. Schmid:
    "Unfaithful Glitch Propagation in Existing Binary Circuit Models";
    IEEE Transactions on Computers, 65 (2016), 3; S. 964 - 978.

    Zusätzliche Informationen

  35. Autor/innen: Matthias Függer, E182 - 2; Ulrich Schmid, E182 - 2

    M Függer, U. Schmid:
    "Reconciling fault-tolerant distributed computing and systems-on-chip";
    Distributed Computing, 24 (2012), 6; S. 323 - 355.

    Zusätzliche Informationen

  36. Autor/innen: Matthias Függer, E182 - 2; Andreas Steininger, E182 - 2; Eric Armengaud, E182 - 2

    M Függer, A. Steininger, E. Armengaud:
    "Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - A Combined Formal and Experimental Approach";
    IEEE Transactions on Industrial Informatics, 5 (2009), 2; S. 132 - 145.

    Zusätzliche Informationen

  37. Autor/innen: Michael Gyimesi, E101 - 6; Andreas Dielacher, E182 - 2; Thomas Handl, E182 - 2; Christian Wittmann

    M. Gyimesi, A. Dielacher, T. Handl, C. Wittmann:
    "An Object-oriented Solution to ARGESIM Benchmark C4 `Dining Philosophers Problem´ implemented with AnyLogic";
    Simulation News Europe SNE, 18 (2008), 1; S. 31 - 32.

  38. Autor/in: Alexander Hanzlik, E182 - 1

    A. Hanzlik:
    "SIDERA - a Simulation Model for Time-Triggered Distributed Systems";
    International Review on Computers and Software (IRECOS), 1 (2006), 3; S. 181 - 193.

    Zusätzliche Informationen

  39. Autor/in: Alexander Hanzlik, E182 - 1

    A. Hanzlik:
    "Stability and Performance Analysis of Clock Synchronization in FlexRay";
    International Review on Computers and Software (IRECOS), 1 (2006), 2; S. 146 - 155.

    Zusätzliche Informationen

  40. Autor/innen: Wolfgang Herzner, ARC Seibersdorf; Bernhard Huber, E182 - 1; Csertan György, Budapest University; András Balogh, Budapest University

    W. Herzner, B. Huber, C. György, A. Balogh:
    "The DECOS Tool-Chain: Model-Based Development of Distributed Embedded Safety-Critical Real-Time Systems";
    ERCIM NEWS, 67 (2006), S. 22 - 24.

    Zusätzliche Informationen

  41. Autor/innen: Michael Hofbauer, E354; Kurt Schweiger, E354; Horst Dietrich, E354; Horst Zimmermann, E354; K.O. Voss, GSI Darmstadt; B Merk, GSI Darmstadt; Ulrich Schmid, E182 - 2; Andreas Steininger, E182 - 2

    M. Hofbauer, K. Schweiger, H. Dietrich, H. Zimmermann, K.O. Voss, B Merk, U. Schmid, A. Steininger:
    "Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating Through a 90 nm Bulk CMOS Inverter Chain";
    IEEE Transactions on Nuclear Science, vol 59 (2012), S. 2778 - 2784.

  42. Autor/innen: Michael Hofbauer, E354; Kurt Schweiger, E354; Horst Zimmermann, E354; Ulrich Giesen; Frank Langner; Ulrich Schmid, E182 - 2; Andreas Steininger, E182 - 2

    M. Hofbauer, K. Schweiger, H. Zimmermann, U. Giesen, F. Langner, U. Schmid, A. Steininger:
    "Supply Voltage Dependent On-Chip Single-Event Transient Pulse Shape Measurements in 90-nm Bulk CMOS Under Alpha Irradiation";
    IEEE Transactions on Nuclear Science, 60 (2013), 4; S. 2640 - 2646.

    Zusätzliche Informationen

  43. Autor/innen: Xiowang Huang, Stony Brook U; Justin Seyster, Stony Brook U; Sean Callanan, Stony Brook U; Ketan Dixit, Stony Brook U; Radu Grosu, E182 - 1; Scott A. Smolka, Stony Brook U; Scott D. Stoller, Stony Brook U; Erez Zadok, Stony Brook U

    X. Huang, J. Seyster, S. Callanan, K. Dixit, R. Grosu, S. Smolka, S. Stoller, E. Zadok:
    "Software monitoring with controllable overhead";
    International Journal on Software Tools for Technology Transfer, 14 (2012), 3; S. 327 - 347.

    Zusätzliche Informationen

  44. Autor/innen: Bernhard Huber; Wilfried Elmenreich, E182 - 1

    B. Huber, W. Elmenreich:
    "Wireless Time-Triggered Real-Time Communication";
    Telematik, 3-4 (2004), S. 44 - 50.

    Zusätzliche Informationen

  45. Autor/innen: Benedikt Huber, E182 - 1; Wolfgang Puffitsch, E182 - 1; Martin Schoeberl

    B. Huber, W. Puffitsch, M. Schoeberl:
    "Worst-case execution time analysis-driven object cache design";
    Concurrency and Computation: Practice and Experience, Volume 24 Issue 8 (2012), 24/8; S. 753 - 771.

    Zusätzliche Informationen

  46. Autor/innen: Martin Hutle, E182 - 2; Dahlia Malkhi; Ulrich Schmid, E182 - 2; Lidong Zhou

    M. Hutle, D. Malkhi, U. Schmid, L. Zhou:
    "Chasing the Weakest System Model for Implementing Omega and Consensus";
    IEEE Transactions on Dependable and Secure Computing, 6 (2009), 4; S. 269 - 279.

    Zusätzliche Informationen

  47. Autor/innen: Mirko Jakovljevic; Martin Schlager, E182 - 1; Markus Plankensteiner; Stefan Poledna, E182 - 1

    M. Jakovljevic, M. Schlager, M. Plankensteiner, S. Poledna:
    "Safety Relevant Automotive Electronic Solutions";
    Automotive Electronics International, March (2004), S. 21 - 23.

    Zusätzliche Informationen

  48. Autor/innen: Mirko Jakovljevic; Martin Schlager, E182 - 1; Markus Plankensteiner; Stefan Poledna, E182 - 1

    M. Jakovljevic, M. Schlager, M. Plankensteiner, S. Poledna:
    "Sicherheitsrelevante elektronische Lösungen im Automobil";
    Automotive Elektronics, extra (2004), März; S. 50 - 53.

    Zusätzliche Informationen

  49. Autor/innen: Roland Kammerer, E182 - 1; Roman Obermaisser, Universität Siegen; Bernhard Frömel, E182 - 1

    R. Kammerer, R. Obermaisser, B. Frömel:
    "A router for the containment of timing and value failures in CAN";
    EURASIP Journal on Embedded Systems, 2012 (2012), 4.

    Zusätzliche Informationen

  50. Autor/innen: Susanne Kandl, E182 - 1; Sandeep Chandrashekar

    S. Kandl, S. Chandrashekar:
    "Reasonability of MC/DC for Safety-Relevant Software Implemented in Programming Languages with Short-Circuit Evaluation";
    Computing, 607 (2014).

    Zusätzliche Informationen

  51. Autor/innen: Raimund Kirner, E182 - 1; Susanne Kandl, E182 - 1

    R. Kirner, S. Kandl:
    "Test Coverage Analysis and Preservation for Requirements-Based Testing of Safety-Critical Systems";
    ERCIM NEWS, 75 (2008), 75; S. 40 - 41.

    Zusätzliche Informationen

  52. Autor/innen: Raimund Kirner, E182 - 1; Jens Knoop, E185 - 1; Adrian Prantl, E185 - 1; Markus Schordan; Albrecht Kadlec, E182 - 1

    R. Kirner, J. Knoop, A. Prantl, M Schordan, A. Kadlec:
    "Beyond Loop Bounds: Comparing Annotation Languages for Worst-Case Time Analysis";
    Journal of Software and Systems Modeling (online-edition), oB (2010).

    Zusätzliche Informationen

  53. Autor/innen: Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1; Adrian Prantl, E185 - 1

    R. Kirner, P. Puschner, A. Prantl:
    "Transforming Flow Information during Code Optimization for Timing Analysis";
    Real-Time Systems, 45 (2010), 1-2; S. 72 - 105.

    Zusätzliche Informationen

  54. Autor/innen: Igor Konnov, E184 - 4; Helmut Veith, E184 - 4; Josef Widder, E182 - 2

    I. Konnov, V. Veith, J. Widder:
    "On the completeness of bounded model checking for threshold-based distributed algorithms: Reachability";
    Information and Computation, 252 (2017), S. 95 - 109.

    Zusätzliche Informationen

  55. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "Time Triggered Architecture";
    ERCIM NEWS, 1 (2003), 52; S. 24 - 25.

  56. Autor/innen: Hermann Kopetz, E182 - 1; Astrit Ademaj, E182 - 1; Alexander Hanzlik, E182 - 1

    H. Kopetz, A. Ademaj, A. Hanzlik:
    "Combination of clock-state and clock-rate correction in fault-tolerant distributed systems";
    Real-Time Systems, 33 (2006), S. 139 - 173.

    Zusätzliche Informationen

  57. Autor/innen: Hermann Kopetz, E182 - 1; Günther Bauer, E182 - 1

    H. Kopetz, G. Bauer:
    "The Time-Triggered Architecture";
    Proceedings of the IEEE, 91 (2003), 1; S. 112 - 126.

    Zusätzliche Informationen

  58. Autor/innen: Hermann Kopetz, E182 - 1; Michael Holzmann, E182 - 1; Wilfried Elmenreich, E182 - 1

    H. Kopetz, M. Holzmann, W. Elmenreich:
    "A Universal Smart Transducer Interface: TTP/A";
    International Journal of Computer System, Science & Engineering, 16 (2001), 2; S. 71 - 77.

    Zusätzliche Informationen

  59. Autor/innen: Hermann Kopetz, E182 - 1; Roman Obermaisser, Universität Siegen

    H. Kopetz, R. Obermaisser:
    "Temporal Composability";
    IEE's Computing & Control Engineering Journal (eingeladen), 13 (2002), 4; S. 156 - 162.

    Zusätzliche Informationen

  60. Autor/innen: Hermann Kopetz, E182 - 1; Roman Obermaisser, Universität Siegen; Ulrich Schmid, E182 - 2

    H. Kopetz, R. Obermaisser, U. Schmid:
    "Dependable Embedded Systems Research at TU Vienna";
    Elektrotechnik und Informationstechnik (e&i) (eingeladen), 1 (2005), 1; S. 33 - 37.

    Zusätzliche Informationen

  61. Autor/innen: Voin Legourski, E182 - 2; Yilin Huang; Ondrej Cevan; Felix Breitenecker, E101 - 6

    V. Legourski, Y. Huang, O. Cevan, F. Breitenecker:
    "Statechart Modelling for ARGESIM Benchmark C10 `Dining Philosophers Problem II´ using Simulink/Stateflow";
    Simulation News Europe SNE, 18 (2008), 1; S. 39 - 40.

  62. Autor/innen: Thomas Losert, E182 - 1; Martin Schlager, E182 - 1; Wilfried Elmenreich, E182 - 1

    T. Losert, M. Schlager, W. Elmenreich:
    "Fault-Tolerant Compensation of the Propagation Delay for Hard Real-Time Systems";
    Journal of Advanced Computational Intelligence and Intelligent Informatics, 9 (2005), 4; S. 346 - 352.

  63. Autor/innen: Reinhard Maier; Günther Bauer, E182 - 1; Georg Stöger; Stefan Poledna, E182 - 1

    R. Maier, G. Bauer, G. Stöger, S. Poledna:
    "Time-Triggered Architecture: A Consistent Computing Platform";
    IEEE Micro, 22 (2002), 4; S. 36 - 45.

    Zusätzliche Informationen

  64. Autor/innen: Dietmar Maurer, E182 - 2; Valentina Salapura, E182 - 2; Michael Gschwind

    D. Maurer, V. Salapura, M. Gschwind:
    "FPGA prototyping of a RISC processor core for embedded applications ";
    IEEE Transactions on Computers, 9 (2001), S. 241 - 250.

    Zusätzliche Informationen

  65. Autor/innen: Marian Molnar, E360; D Donoval; J. Kuzmik; J Marek; A Chvala; P. Pribytny; Vaclav Mikolasek, E182 - 1; K. Rendek; Vassil Palankovski, E360

    M. Molnar, D. Donoval, J. Kuzmik, J. Marek, A. Chvala, P. Pribytny, V. Mikolasek, K. Rendek, V. Palankovski:
    "Simulation Study of Interface Traps and Bulk Traps in n++GaN/InAlN/AlN/GaN High Electron Mobility Transistors";
    Applied Surface Science, 312 (2014), S. 157 - 161.

    Zusätzliche Informationen

  66. Autor/in: Heinrich Moser, E182 - 2

    H. Moser:
    "Towards a real-time distribiuted computing model";
    Theoretical Computer Science, 410 (2008), 6-7; S. 631 - 659.

    Zusätzliche Informationen

  67. Autor/innen: Heinrich Moser, E182 - 2; Ulrich Schmid, E182 - 2

    H. Moser, U. Schmid:
    "Reconciling fault-tolerant distributed algorithms and real-time computing";
    Distributed Computing, 27 (2014), 3; S. 203 - 230.

    Zusätzliche Informationen

  68. Autor/innen: Abhishek Murthy, Stony Brook U; Ezio Bartocci, E182 - 1; Flavio H. Fenton, Cornell U.; James Glimm, Stony Brook U; Richard A. Gray, FDA; Elizabeth Cherry, Rochester Inst.; Scott A. Smolka, Stony Brook U; Radu Grosu, E182 - 1

    A. Murthy, E. Bartocci, F. Fenton, J. Glimm, R. Gray, E. Cherry, S. Smolka, R. Grosu:
    "Curvature Analysis of Cardiac Excitation Wavefronts";
    IEEE/ACM Transactions on Computational Biology and Bioinformatics, 10 (2013), 2; S. 323 - 336.

    Zusätzliche Informationen

  69. Autor/innen: Thomas Nowak; Matthias Függer, E182 - 2; Alexander Kößler, E182 - 2

    T. Nowak, M Függer, A. Kößler:
    "On the performance of a retransmission-based synchronizer";
    Theoretical Computer Science, 509 (2013), S. 25 - 39.

  70. Autor/innen: Roman Obermaisser, Universität Siegen; Hermann Kopetz, E182 - 1; Sibylle Kuster, E015

    R. Obermaisser, H. Kopetz, S. Kuster:
    "GENESYS (GENeric Embedded SYStem) - A Candidate for an ARTEMIS Cross-Domain Reference Architecture for Embedded Systems";
    ARTEMIS Magazine, 5 (2009), S. 32 - 34.

    Zusätzliche Informationen

  71. Autor/innen: Roman Obermaisser, Universität Siegen; Philipp Peti, E182 - 1; Bernhard Huber, E182 - 1; Christian El Salloum, E182 - 1

    R. Obermaisser, P. Peti, B. Huber, C. El Salloum:
    "DECOS: An Integrated Time-Triggered Architecture";
    Journal e&i: Elektrotechnik und Informationstechnik, 3 (2006), S. 83 - 95.

    Zusätzliche Informationen

  72. Autor/innen: Christof Pitter, E182 - 1; Martin Schoeberl, E182 - 1

    C. Pitter, M. Schoeberl:
    "A real-time Java chip-multiprocessor";
    ACM Transactions on Embedded Computing Systems, 10 (2010), 1; S. 1 - 34.

    Zusätzliche Informationen

  73. Autor/innen: Stefan Poledna, E182 - 1; Peter Barrett; Alan Burns; Andy Wellings

    S. Poledna, P. Barrett, A. Burns, A. Wellings:
    "Replica Determinism and Flexible Scheduling in Hard Real-Time Dependable Systems";
    IEEE Transactions on Computers, 49 (2000), 2; S. 100 - 111.

    Zusätzliche Informationen

  74. Autor/innen: Thomas Polzer, E182 - 2; Robert Najvirt, E182 - 2; Florian Beck, E182 - 2; Andreas Steininger, E182 - 2

    T. Polzer, R. Najvirt, F. Beck, A. Steininger:
    "On the Appropriate Handling of Metastable Voltages in FPGAs";
    Journal of Circuits, Systems, and Computers, 25 (2015), 3; S. 1640020-1 - 1640020-25.

    Zusätzliche Informationen

  75. Autor/innen: Peter Puschner, E182 - 1; Alan Burns

    P. Puschner, A. Burns:
    "A Review of Worst-Case Execution-Time Analysis";
    Real-Time Systems, 18 (2000), 2/3; S. 115 - 128.

    Zusätzliche Informationen

  76. Autor/innen: Babak Rahbaran, E182 - 2; Matthias Függer, E182 - 2; Andreas Steininger, E182 - 2

    B. Rahbaran, M Függer, A. Steininger:
    "Embedded Real-Time-Tracer -- An Approach with IDE";
    Telematik, 3-4 (2004), S. 16 - 20.

    Zusätzliche Informationen

  77. Autor/innen: Babak Rahbaran, E182 - 2; Andreas Steininger, E182 - 2

    B. Rahbaran, A. Steininger:
    "Is Asynchronous Logic More Robust Than Synchronous Logic?";
    IEEE Transactions on Dependable and Secure Computing, 6 (2009), 4; S. 282 - 294.

    Zusätzliche Informationen

  78. Autor/innen: Arvind Nath Rapaka; Wilfried Elmenreich, E182 - 1; Donald Wunsch

    A. N. Rapaka, W. Elmenreich, D. Wunsch:
    "TTP/A Protocol and Design";
    Circuit Cellar, (2004), 164; S. 12 - 21.

    Zusätzliche Informationen

  79. Autor/innen: Thomas Reinbacher, E182; Jörg Brauer; Martin Horauer; Andreas Steininger, E182 - 2; Stefan Kowalewski

    T. Reinbacher, J. Brauer, M. Horauer, A. Steininger, S. Kowalewski:
    "Runtime verification of microcontroller binary code";
    Science of Computer Programming, 80 (2014), S. 109 - 129.

    Zusätzliche Informationen

  80. Autor/innen: Thomas Reinbacher, E182; Matthias Függer, E182 - 2; Jörg Brauer

    T. Reinbacher, M Függer, J. Brauer:
    "Runtime verification of embedded real-time systems";
    Formal Methods in System Design, Nov 2013 (2013), 10703; S. 1 - 37.

    Zusätzliche Informationen

  81. Autor/innen: Stefan Resch, Thales; Andreas Steininger, E182 - 2; Christoph Scherrer, Thales

    S. Resch, A. Steininger, C. Scherrer:
    "A Composable Real-Time Architecture for Replicated Railway Applications";
    Journal of Systems Architecture, 61 (2015), 9; S. 472 - 485.

    Zusätzliche Informationen

  82. Autor/innen: Peter Robinson, E182 - 2; Ulrich Schmid, E182 - 2

    P. Robinson, U. Schmid:
    "The Asynchronous Bounded-Cycle Model";
    Theoretical Computer Science, 412 (2011), 40; S. 5580 - 5601.

    Zusätzliche Informationen

  83. Autor/innen: Christoph Scherrer, E182 - 2; Andreas Steininger, E182 - 2

    C. Scherrer, A. Steininger:
    "Dealing With Dormant Faults in an Embedded Fault-Tolerant Computer System";
    IEEE Transactions on Reliability, 52 (2003), 4; S. 512 - 522.

    Zusätzliche Informationen

  84. Autor/innen: Martin Schlager, E182 - 1; Roman Obermaisser, Universität Siegen; Wilfried Elmenreich, E182 - 1

    M. Schlager, R. Obermaisser, W. Elmenreich:
    "A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture";
    Lecture Notes in Computer Science, 4761 (2007), S. 159 - 170.

    Zusätzliche Informationen

  85. Autor/innen: Ulrich Schmid, E182 - 2; Klaus Schossmaier, E183 - 1

    U. Schmid, K. Schossmaier:
    "Interval-based clock synchronization with optimal precision.";
    Information and Computation, 186 (2003), 1; S. 36 - 77.

  86. Autor/innen: Ulrich Schmid, E182 - 2; Andreas Steininger, E182 - 2; Manfred Sust

    U. Schmid, A. Steininger, M. Sust:
    "FIT-IT Projekt DARTS: Dezentrale fehlertolerante Taktgenerierung";
    Elektrotechnik und Informationstechnik (e&i), Heft 1-2 (2007), S. 3 - 8.

    Zusätzliche Informationen

  87. Autor/innen: Ulrich Schmid, E182 - 2; Bettina Weiss, E182 - 2; Idit Keidar

    U. Schmid, B. Weiss, I. Keidar:
    "Impossibility Results and Lower Bounds For Consensus Under Link Failures";
    SIAM JOURNAL ON COMPUTING, 38 (2009), 5; S. 1912 - 1951.

    Zusätzliche Informationen

  88. Autor/in: Martin Schoeberl, E182 - 1

    M. Schoeberl:
    "A Java processor architecture for embedded real-time systems";
    Journal of Systems Architecture, Volume 54, Issues 1-2 (2008), S. 265 - 286.

    Zusätzliche Informationen

  89. Autor/in: Martin Schoeberl, E182 - 1

    M. Schoeberl:
    "Mission Modes for Safety Critical Java";
    Lecture Notes in Computer Science, 4761 (2007), S. 105 - 113.

    Zusätzliche Informationen

  90. Autor/in: Martin Schoeberl, E182 - 1

    M. Schoeberl:
    "Scheduling of Hard Real-Time Garbage Collection";
    Real-Time Systems, 45 (2010), 3; S. 176 - 213.

    Zusätzliche Informationen

  91. Autor/innen: Martin Schoeberl; Sahar Abbaspour; Benny Akesson; Neil Audsley; Raffaele Capasso; Jamie Garside; Kees Goossens; Sven Goossens; Scott Hansen; Reinhold Heckmann; Stefan Hepp, E185 - 1; Benedikt Huber, E182 - 1; Alexander Jordan, E185 - 1; Evangelia Kasapaki; Jens Knoop, E185 - 1; Yonghui Li; Daniel Prokesch, E182 - 1; Wolfgang Puffitsch, DTU; Peter Puschner, E182 - 1; André Rocha; Cláudio Silva; Jens Sparso, DTU Kopenhagen; Alessandro Tocchi

    M. Schoeberl, S. Abbaspour, B. Akesson, N. Audsley, R. Capasso, J. Garside, K. Goossens, S. Goossens, S. Hansen, R. Heckmann, S Hepp, B. Huber, A. Jordan, E. Kasapaki, J. Knoop, Y. Li, D. Prokesch, W. Puffitsch, P. Puschner, A. Rocha, C Silva, J. Sparso, A. Tocchi:
    "T-CREST: Time-Predictable Multi-Core Architecture for Embedded Systems";
    Journal of Systems Architecture, Volume 61 (2015), Issue 9; S. 449 - 471.

    Zusätzliche Informationen

  92. Autor/innen: Martin Schoeberl; Benedikt Huber, E182 - 1; Wolfgang Puffitsch, E182 - 1

    M. Schoeberl, B. Huber, W. Puffitsch:
    "Data cache organization for accurate timing analysis";
    Real-Time Systems, 49 (2013), 1; S. 1 - 28.

    Zusätzliche Informationen

  93. Autor/innen: Martin Schoeberl, E182 - 1; Wolfgang Puffitsch, E182 - 1; Rasmus Pedersen; Benedikt Huber, E182 - 1

    M. Schoeberl, W. Puffitsch, R. Pedersen, B. Huber:
    "Worst-case execution time analysis for a Java processor";
    Software: Practice and Experience, 40 (2010), 6; S. 507 - 542.

    Zusätzliche Informationen

  94. Autor/innen: Justin Seyster, Stony Brook U; Ketan Dixit, Stony Brook U; Xiowang Huang, Stony Brook U; Radu Grosu, E182 - 1; Klaus Havelund, JPL; Scott A. Smolka, Stony Brook U; Scott D. Stoller, Stony Brook U; Erez Zadok, Stony Brook U

    J. Seyster, K. Dixit, X. Huang, R. Grosu, K Havelund, S. Smolka, S. Stoller, E. Zadok:
    "InterAspect: aspect-oriented instrumentation with GCC";
    Formal Methods in System Design, 41 (2012), 3; S. 295 - 320.

    Zusätzliche Informationen

  95. Autor/innen: Muhammad Shafique, E182 - 2; Anton Ivanov, KIT; Benjamin Vogel, KIT; Jörg Henkel, KIT

    M. Shafique, A. Ivanov, B. Vogel, J. Henkel:
    "Scalable Power Management for On-Chip Systems with Malleable Applications";
    IEEE Transactions on Computers, 65 (2016), 11; S. 3398 - 3412.

    Zusätzliche Informationen

  96. Autor/innen: Muhammad Shafique, E182 - 2; Muhammad Usman Karim Khan, IBM; Jörg Henkel, KIT

    M. Shafique, M. Usman Karim Khan, J. Henkel:
    "Content-Aware Low-Power Configurable Aging Mitigation for SRAM Memories";
    IEEE Transactions on Computers, 65 (2016), 12; S. 3617 - 3630.

    Zusätzliche Informationen

  97. Autor/in: Wilfried Steiner, E182 - 1

    W. Steiner:
    "Advancements in Dependable Time-Triggered Communication";
    Lecture Notes in Computer Science, 4761 (2007), S. 57 - 66.

    Zusätzliche Informationen

  98. Autor/innen: Wilfried Steiner, E182 - 1; Michael Paulitsch, E182 - 1; Hermann Kopetz, E182 - 1

    W. Steiner, M. Paulitsch, H. Kopetz:
    "The TTA's Approach to Resilience after Transient Upsets";
    Real-Time Systems, 32 (2006), 3; S. 213 - 233.

    Zusätzliche Informationen

  99. Autor/in: Andreas Steininger, E182 - 2

    A. Steininger:
    "Testing and Built-in-Self-Test - A Survey";
    Journal of Systems Architecture, 46 (2000), S. 721 - 747.

  100. Autor/innen: Andreas Steininger, E182 - 2; Gottfried Fuchs, E182 - 2

    A. Steininger, G. Fuchs:
    "VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation";
    Journal of Electrical and Computer Engineering, Clock/Frequency Generation Circuits and Systems (2011), 936712; S. 23.

    Zusätzliche Informationen

  101. Autor/innen: Andreas Steininger, E182 - 2; Christoph Scherrer, E182 - 2

    A. Steininger, C. Scherrer:
    "Identifying Efficient Combinations of Error Detection Mechanisms Based on Results of Fault-Injection Experiments";
    IEEE Transactions on Computers, 51 (2002), 2; S. 235 - 239.

  102. Autor/innen: Andreas Steininger, E182 - 2; Christoph Scherrer, E182 - 2

    A. Steininger, C. Scherrer:
    "Vom Lenkrad zum Joystick";
    Elektrotechnik und Informationstechnik (e&i), 11 (2000), S. 714 - 720.

  103. Autor/innen: Andreas Steininger, E182 - 2; Peter Tummeltshammer, E182 - 2

    A. Steininger, P Tummeltshammer:
    "Replicated processors on a single die - How independently do they fail?";
    Journal e&i: Elektrotechnik und Informationstechnik, 128 (2011), S. 245 - 250.

    Zusätzliche Informationen

  104. Autor/innen: Andreas Steininger, E182 - 2; Horst Zimmermann, E354; Axel Jantsch, E384; Michael Hofbauer, E354; Ulrich Schmid, E182 - 2; Kurt Schweiger, E354; Savulimedu Veeravall Varadan, E182 - 2

    A. Steininger, H. Zimmermann, A. Jantsch, M. Hofbauer, U. Schmid, K. Schweiger, S. Varadan:
    "Building reliable systems-on-chip in nanoscale technologies";
    E&I Elektrotechnik und Informationstechnik, 132 (2015), 6; S. 301 - 306.

    Zusätzliche Informationen

  105. Autor/innen: Shabnam Michele Tauböck, E101 - 6; Philipp Jahn, E182 - 1; Thomas Polzer, E182 - 2; Alexandra Schuster

    S. Tauböck, P. Jahn, T. Polzer, A. Schuster:
    "An Object-oriented DEV Approach to ARGESIM Benchmark C16 `Restaurant Business Dynamics´ using Enterprise Dynamics";
    Simulation News Europe SNE, 18 (2008), 1; S. 41 - 42.

  106. Autor/innen: Karl Thaller, E182 - 2; Andreas Steininger, E182 - 2

    K. Thaller, A. Steininger:
    "A Transparent Online Memory Test for Simultaneous Detection of Functional Faults and Soft Errors in Memories";
    IEEE Transactions on Reliability, 52 (2003), 4; S. 413 - 422.

    Zusätzliche Informationen

  107. Autor/innen: Bernd Thallner, E182 - 2; Heinrich Moser, E182 - 2; Ulrich Schmid, E182 - 2

    B. Thallner, H. Moser, U. Schmid:
    "Topology Control for Fault-Tolerant Communication in Wireless Ad Hoc Networks";
    Wireless Networks, 16 (2010), 21; S. 388 - 404.

    Zusätzliche Informationen

  108. Autor/innen: Savulimedu Veeravall Varadan, E182 - 2; Thomas Polzer, E182 - 2; Ulrich Schmid, E182 - 2; Andreas Steininger, E182 - 2; Michael Hofbauer, E354; Kurt Schweiger, E354; Horst Dietrich, E354; Kerstin Schneider-Hornstein, E354; Horst Zimmermann, E354; Kay-Obbe Voss, GSI; Bruno Merk, GSI; Michael Hajek, E141 - STP

    S. Varadan, T. Polzer, U. Schmid, A. Steininger, M. Hofbauer, K. Schweiger, H. Dietrich, K. Schneider-Hornstein, H. Zimmermann, K. Voss, B. Merk, M. Hajek:
    "An infrastructure for accurate characterization of single-event transients in digital circuits";
    Microprocessors and Microsystems, 37 (2013), S. 772 - 791.

    Zusätzliche Informationen

  109. Autor/innen: Ingomar Wenzel, E182 - 1; Raimund Kirner, E182 - 1; Bernhard Rieder, E182 - 1; Peter Puschner, E182 - 1

    I. Wenzel, R. Kirner, B. Rieder, P. Puschner:
    "Cross-Platform Verification Framework for Embedded Systems";
    Lecture Notes in Computer Science, 4761 (2007), S. 137 - 148.

    Zusätzliche Informationen

  110. Autor/innen: Josef Widder, E182 - 2; Martin Biely, E182 - 2

    J. Widder, M. Biely:
    "Optimal Message-Driven Implementations of Omega with Mute Processes";
    ACM Transactions on Autonomous and Adaptive Systems., 4 (2009), 1; S. ?.

    Zusätzliche Informationen

  111. Autor/innen: Josef Widder, E184 - 4; Martin Biely, EPFL; Günther Gridling, E183 - 1; Bettina Weiss, E182 - 2; Jean-Paul Blanquart, Astrium Satellites

    J. Widder, M. Biely, G. Gridling, B. Weiss, J. Blanquart:
    "Consensus in the presence of mortal Byzantine faulty processes";
    Distributed Computing, 24 (2012), 6; S. 299 - 321.

    Zusätzliche Informationen

  112. Autor/innen: Josef Widder, E182 - 2; Ulrich Schmid, E182 - 2

    J. Widder, U. Schmid:
    "The Theta-Model: achieving synchrony without clocks";
    Distributed Computing, 22 (2009), 1; S. 29 - 47.

    Zusätzliche Informationen

  113. Autor/in: Martin Zeiner, E182 - 2

    M. Zeiner:
    "On a family of $q$-binomial distributions";
    Mathematica Slovaca, 64 (2014), 2; S. 479 - 510.

    Zusätzliche Informationen


Editorials in wiss. Zeitschriften


  1. Autor/innen: Ezio Bartocci, E182 - 1; Luca Bortolussi, Univ. of Trieste; Scott A. Smolka, Stony Brook U

    E. Bartocci, L. Bortolussi, S. Smolka:
    "Hybrid Systems and Biology";
    Information and Computation, 236 (2014), S. 1 - 2.

  2. Autor/innen: Ezio Bartocci, E182 - 1; C.R. Ramakrishnan

    E. Bartocci, C. Ramakrishnan:
    "Preface of the special issue on Model Checking of Software - Selected papers of the 20th International SPIN Symposium on Model Checking of Software";
    International Journal on Software Tools for Technology Transfer, 18 (2016), S. 355 - 357.

    Zusätzliche Informationen


Buchbeiträge


  1. Autor/innen: Walter Binder; Martin Schoeberl, E182 - 1; Philippe Moret; Alex Villazón

    W. Binder, M. Schoeberl, P. Moret, A. Villazón:
    "Cross-profiling for Java processors";
    in: "Software: Practice and Experience", herausgegeben von: Wiley InterScience; John Wiley and Sons, 2009, ISSN: 0038-0644, S. 1439 - 1465.

    Zusätzliche Informationen

  2. Autor/innen: Sven Bünte, E182 - 1; Michael Zolda, E182 - 1; Raimund Kirner, E182 - 1

    S. Bünte, M. Zolda, R. Kirner:
    "Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility";
    in: "Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility", IGI Global, 2011, ISBN: 9781609600860, S. 110 - 129.

    Zusätzliche Informationen

  3. Autor/innen: Andrea Ceccarelli, UNIFI; Andrea Bondavalli, UNIFI; Bernhard Frömel, E182 - 1; Oliver Höftberger, E182 - 1; Hermann Kopetz, E182 - 1

    A. Ceccarelli, A. Bondavalli, B. Frömel, O. Höftberger, H. Kopetz:
    "Basic Concepts on Systems of Systems";
    in: "Cyber-Physical Systems of Systems, Foundations - A Conceptual Model and Some Derivations: The AMADEOS Legacy", 10099; Springer International Publishing, 2016, ISBN: 978-3-319-47589-9, S. 1 - 39.

    Zusätzliche Informationen

  4. Autor/innen: Andrea Ceccarelli, UNIFI; Francesco Brancati, Resiltech S.R.L.; Bernhard Frömel, E182 - 1; Oliver Höftberger, E182 - 1

    A. Ceccarelli, F. Brancati, B. Frömel, O. Höftberger:
    "Time and Resilient Master Clocks in Cyber-Physical Systems";
    in: "Cyber-Physical Systems of Systems, Foundations - A Conceptual Model and Some Derivations: The AMADEOS Legacy", 10099; Springer International Publishing, 2016, ISBN: 978-3-319-47589-9, S. 165 - 185.

    Zusätzliche Informationen

  5. Autor/innen: Christian El Salloum, E182 - 1; Kenan Bilic

    C. El Salloum, K. Bilic:
    "Time-Triggered Communication (Book Chapter on FlexRay)";
    in: "Time-Triggered Communication", CRC Press, 2011, (eingeladen), ISBN: 978-1-4398-4661-2, S. 121 - 152.

  6. Autor/innen: Wilfried Elmenreich, E182 - 1; Raimund Kirner, E182 - 1

    W. Elmenreich, R. Kirner:
    "A Robust Certainty Grid Algorithm for Robotic Vision";
    in: "Intelligent Systems at the Service of Mankind", UBooks Verlag, Augsburg, Deutschland, 2003, ISBN: 3-935798-25-3, S. 67 - 78.

    Zusätzliche Informationen

  7. Autor/innen: Wilfried Elmenreich, E182 - 1; Philipp Peti, E182 - 1

    W. Elmenreich, P. Peti:
    "Distributed Sensor Fusion Networks";
    in: "Intelligent Engineering Systems at the Service of Mankind", UBooks Verlag, Augsburg, Deutschland, 2003, ISBN: 3-935798-25-3, S. 335 - 347.

    Zusätzliche Informationen

  8. Autor/innen: Wilfried Elmenreich, E182 - 1; Stefan Pitzek, E182 - 1
    Andere beteiligte Personen: Wilfried Elmenreich, E182 - 1; J. A. Tenreiro Machado, ISEP, Porto; Imre J. Rudas

    W. Elmenreich, S. Pitzek:
    "Smart Transducers - Principles, Communications and Configuration";
    in: "Intelligent Systems at the Service of Mankind, Volume II", W. Elmenreich, J.A.T. Machado, I. J. Rudas (Hrg.); UBooks Verlag, Augsburg, 2005, ISBN: 3-86608-052-2, S. 175 - 186.

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  9. Autor/innen: Bernhard Frömel, E182 - 1; Hermann Kopetz, E182 - 1

    B. Frömel, H. Kopetz:
    "Interfaces in Evolving Cyber-Physical Systems-of-Systems";
    in: "Cyber-Physical Systems of Systems, Foundations - A Conceptual Model and Some Derivations: The AMADEOS Legacy", 10099; Springer International Publishing, 2016, ISBN: 978-3-319-47589-9, S. 40 - 72.

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  10. Autor/innen: Annu Gmeiner, E184 - 4; Igor Konnov, E184 - 4; Ulrich Schmid, E182 - 2; Helmut Veith, E184 - 4; Josef Widder, E184 - 4

    A. Gmeiner, I. Konnov, U. Schmid, V. Veith, J. Widder:
    "Tutorial on Parameterized Model Checking of Fault-Tolerant Distributed Algorithms";
    in: "Formal Methods for Executable Software Models", Springer, 2014, (eingeladen), ISBN: 978-3-319-07316-3, S. 122 - 171.

  11. Autor/innen: Karl Hendling, E389; Thomas Losert, E182 - 1; Martin Jandl, E384
    Andere beteiligte Person: Wolfgang Huber, E182 - 2

    K. Hendling, T. Losert, M. Jandl:
    "An Intelligent Interference-Minimizing Routing Algorithm";
    in: "Intelligent Systems at the Service of Mankind - Volume II", W. Huber (Hrg.); Ubooks, Augsburg, 2006, ISBN: 3866080522, S. 187 - 204.

  12. Autor/innen: Bernhard Huber, E182 - 1; Roman Obermaisser, Universität Siegen

    B. Huber, R. Obermaisser:
    "Platform Modeling in Safety-Critical Embedded Systems";
    in: "Intelligent Technical Systems", herausgegeben von: Springer; Springer, LNEE Vol. 38, 2009, ISBN: 978-1-4020-9822-2, S. 145 - 158.

    Zusätzliche Informationen

  13. Autor/in: Roland Kammerer, E182 - 1

    R. Kammerer:
    "TTCAN";
    in: "Time-Triggered Communication", CRC Press, 2011, (eingeladen), ISBN: 9781439846612, S. 223 - 245.

  14. Autor/in: Susanne Kandl, E182 - 1

    S. Kandl:
    "Cost Effectiveness of Coverage-Guided Test-Suite Reduction for Safety-Relevant Systems";
    in: "Progress in Systems Engineering (Advances in Intelligent Systems and Computing)", herausgegeben von: Henry Selvaraj, Dawid Zydek, Grzegorz Chmaj (Eds.); Springer International Publishing, Switzerland, 2015, ISBN: 978-3-319-08421-3, S. 595 - 601.

    Zusätzliche Informationen

  15. Autor/innen: Hermann Kopetz, E182 - 1; Günther Bauer, E182 - 1

    H. Kopetz, G. Bauer:
    "Time Triggered Communication Networks";
    in: "Industrial Information Technology Handbook", CRC Press, Boca Raton,FL 33431, USA, 2005, ISBN: 0-8493-1985-4.

  16. Autor/innen: Hermann Kopetz, E182 - 1; Günther Bauer, E182 - 1; Wilfried Steiner, E182 - 1

    H. Kopetz, G. Bauer, W. Steiner:
    "Dependable Time-Triggered Communication";
    in: "The Industrial Communication Technology Handbook", CRC Press, Boca Raton,FL 33431, USA, 2005, ISBN: 0-8493-3077-7.

  17. Autor/innen: Hermann Kopetz, E182 - 1; Andrea Bondavalli, UNIFI; Francesco Brancati, Resiltech S.R.L.; Bernhard Frömel, E182 - 1; Oliver Höftberger, E182 - 1; Sorin Iacob

    H. Kopetz, A. Bondavalli, F. Brancati, B. Frömel, O. Höftberger, S. Iacob:
    "Emergence in Cyber-Physical Systems-of-Systems (CPSoSs)";
    in: "Cyber-Physical Systems of Systems, Foundations - A Conceptual Model and Some Derivations: The AMADEOS Legacy", 10099; Springer International Publishing, 2016, ISBN: 978-3-319-47589-9, S. 73 - 96.

    Zusätzliche Informationen

  18. Autor/innen: Thomas Losert, E182 - 1; Wolfgang Huber, E182 - 2; Karl Hendling, E389; Martin Jandl, E384

    T. Losert, W. Huber, K. Hendling, M. Jandl:
    "A CORBA-Based Architecture for Hard Real-Time Systems";
    in: "Intelligent Systems at the Service of Mankind - Volume II", Ubooks, Augsburg, 2006, ISBN: 3866080522, S. 239 - 254.

  19. Autor/innen: Liana Musat; Markus Hübl; Andi Buzo; Georg Pelz; Susanne Kandl, E182 - 1; Peter Puschner, E182 - 1

    L. Musat, M. Hübl, A. Buzo, G. Pelz, S. Kandl, P. Puschner:
    "Semi-formal Representation of Requirements for Automotive Solutions Using SysML";
    in: "Languages, Design Methods, and Tools for Electronic System Design", Lecture Notes in Electrical Engineering 361; herausgegeben von: Frank Oppenheimer, Julio Luis Medina Pasaje; Springer International Publishing, 2016, ISBN: 978-3-319-24457-0, S. 57 - 81.

    Zusätzliche Informationen

  20. Autor/innen: Roman Obermaisser, Universität Siegen; Christian El Salloum, E182 - 1; Bernhard Huber, E182 - 1; Hermann Kopetz, E182 - 1

    R. Obermaisser, C. El Salloum, B. Huber, H. Kopetz:
    "From a Federated to an Integrated Automotive Architecture";
    in: "IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems", IEEE, 2009, ISSN: 0278-0070, S. 956 - 965.

    Zusätzliche Informationen

  21. Autor/innen: Stefan Pitzek, E182 - 1; Wilfried Elmenreich, E182 - 1

    S. Pitzek, W. Elmenreich:
    "Configuration and Management of Fieldbus Systems";
    in: "The Industrial Communication Technology Handbook", CRC Press, Boca Raton,FL 33431, USA, 2005, ISBN: 0-8493-3077-7, S. 18-1 - 18-20.

  22. Autor/in: Peter Puschner, E182 - 1
    Andere beteiligte Personen: Bernd Kleinjohann; Kane Kim; Lisa Kleinjohann; Achim Rettberg

    P. Puschner:
    "Transforming Execution-Time Boundable Code into Temporally Predictable Code";
    in: "Design and Analysis of Distributed Embedded Systems", B. Kleinjohann, K. Kim, L. Kleinjohann, A. Rettberg (Hrg.); Kluwer Academic Publishers, 2002, S. 163 - 172.

    Zusätzliche Informationen

  23. Autor/innen: Peter Puschner, E182 - 1; Guillem Bernat; Andy Wellings
    Andere beteiligte Personen: Nora Brambilla; Olivier Sparagano; Luc Deneire

    P. Puschner, G. Bernat, A. Wellings:
    "Making Java Hard Real-Time";
    in: "The Annals of the Marie Curie Fellowship Association (MCFA) Volume II", N. Brambilla, O. Sparagano, L. Deneire (Hrg.); Marie Curie Fellowship Association, 2002.

    Zusätzliche Informationen

  24. Autor/in: Martin Schoeberl, E182 - 1

    M. Schoeberl:
    "Time-Predictable Computer Architecture";
    in: "EURASIP Journal on Embedded Systems", herausgegeben von: HIndawi; Hindawi, 2009, 17 S.

    Zusätzliche Informationen

  25. Autor/in: Andreas Steininger, E182 - 2
    Andere beteiligte Person: Andrey Mokhov, Univ Newcastle

    A. Steininger:
    "Fifty Shades of Synchrony";
    in: "This Asynchronous Woirld", A. Mokhov (Hrg.); Newcastle University, Newcastle upon Tyne, 2016, (eingeladen), ISBN: 978-0-7017-0257-1, S. 294 - 300.

    Zusätzliche Informationen

  26. Autor/innen: Peter Tummeltshammer, E182 - 2; James.C Hoe; Markus Pueschel

    P Tummeltshammer, J.C Hoe, M. Pueschel:
    "Time-Multiplexed Multiple Constant Multiplication";
    in: "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems", IEEE, 2007, S. 1551 - 1563.

    Zusätzliche Informationen

  27. Autor/innen: Josef Widder, E182 - 2; Ulrich Schmid, E182 - 2

    J. Widder, U. Schmid:
    "Booting Clock Synchronization in Partially Synchronous Systems with Hybrid Process and Link Failures";
    in: "Distributed Computing", Springer-Verlag, 2007, S. 115 - 140.

    Zusätzliche Informationen


Beiträge in Tagungsbänden


  1. Autor/innen: K. Ambrosch; Christopher Helpa; Jakob Lechner, E182 - 2; Robert Leidenfrost; Thomas Panhofer; Andreas platschek; Stephan Ramberger; Urban Stadler; D Steiner; Harald Trinkl; Christian Widtmann; Martin Delvai, E182 - 2

    K. Ambrosch, C. Helpa, J. Lechner, R. Leidenfrost, T. Panhofer, A. platschek, S. Ramberger, U. Stadler, D. Steiner, H. Trinkl, C. Widtmann, M. Delvai:
    "Design Variety in Hardware/Software Codesign - Implementations of an AES Encoder";
    in: "Austrochip Mikroelektroniktagung", Austrochip 2006, 2006, S. 181 - 188.

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  2. Autor/innen: Eric Armengaud, E182 - 2; Florian Rothensteiner; Andreas Steininger, E182 - 2; Roman Pallierer, E182 - 1; Martin Horauer; Martin Zauner

    E. Armengaud, F Rothensteiner, A. Steininger, R. Pallierer, M. Horauer, M Zauner:
    "A Structured Approach for the Systematic Test of Embedded Automotive Communication Systems";
    in: "Proceedings International Test Conference 2005", IEEE Computer Society, 2005, ISBN: 0-7803-9039-3, S. 21 - 28.

    Zusätzliche Informationen

  3. Autor/innen: Christof Fetzer; Martin Süßkraut; Ulrich Schmid, E182 - 2

    C. Fetzer, M. Süßkraut, U. Schmid:
    "On the Possibility of Consensus in Asynchronous Systems with Finite Average Response Times";
    in: "On the Possibility of Consensus in Asynchronous Systems with Finite Average Response Times", IEEE Computer Society, 2005, S. 271 - 280.

    Zusätzliche Informationen

  4. Autor/innen: Alois Goiser, E389; Samar Khattab, E389; Gerhard Fassl; Ulrich Schmid, E182 - 2

    A. Goiser, S. Khattab, G. Fassl, U. Schmid:
    "A New Robust Interference Reduction Scheme for Low Complexity Direct-Sequence Spread-Spectrum Receivers: Optimization";
    in: "CTRQ-2010", herausgegeben von: IEEE-Explore; IEEE Computer Society, 2010, ISBN: 978-0-7695-4070-2, 5 S.

    Zusätzliche Informationen

  5. Autor/innen: Alois Goiser, E389; Samar Khattab, E389; Gerhard Fassl; Ulrich Schmid, E182 - 2

    A. Goiser, S. Khattab, G. Fassl, U. Schmid:
    "A New Robust Interference Reduction Scheme for Low Complexity Direct-Sequence Spread-Spectrum Receivers: Performance";
    in: "CTRQ-2010", herausgegeben von: IEEE-Explore; IEEE Conference Proceedings, 2010, ISBN: 978-0-7695-4070-2, 7 S.

    Zusätzliche Informationen

  6. Autor/innen: Michael Hofbauer, E354; Kurt Schweiger, E354; Horst Dietrich, E354; Horst Zimmermann, E354; Ulrich Schmid, E182 - 2; B Merk, GSI Darmstadt

    M. Hofbauer, K. Schweiger, H. Dietrich, H. Zimmermann, U. Schmid, B Merk:
    "Single Event Effect Measurements in 90nm CMOS Circuits at the Microbeam Facility for the Project FATAL";
    in: "GSI Scientific Report 2011", GSI Helmholtzzentrum für Schwerionenforschung GmbH, Darmstadt, 2012, ISSN: 0174-0814, S. 424.

  7. Autor/innen: Niklas Holsti; Jan Gustafsson; Guillem Bernat; Clément Ballabriga; Armelle Bonenfant; Roman Bourgade; Hugues Cassé; Daniel Cordes; Albrecht Kadlec, E182 - 1; Raimund Kirner, E182 - 1; Jens Knoop, E185 - 1; Paul Lokuciejewski; Nicholas Merriam; Marianne de Michiel; Adrian Prantl, E185 - 1; Bernhard Rieder, E182 - 1; Christine Rochange; Pascal Sainrat; Markus Schordan, E185 - 1

    N. Holsti, J. Gustafsson, G. Bernat, C. Ballabriga, A. Bonenfant, R. Bourgade, H. Cassé, D. Cordes, A. Kadlec, R. Kirner, J. Knoop, P. Lokuciejewski, N. Merriam, M. de Michiel, A. Prantl, B. Rieder, C. Rochange, P. Sainrat, M. Schordan:
    "WCET Tool Challenge 2008: Report";
    in: "Worst-Case Execution Time Analysis; Proceedings of the 8th International Workshop (WCET 2008)", Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany, 2008, ISBN: 978-3-939897-10-1, 23 S.

    Zusätzliche Informationen

  8. Autor/innen: Roman Pallierer, E182 - 1; Martin Horauer; Martin Zauner; Andreas Steininger, E182 - 2; Eric Armengaud, E182 - 2; Florian Rothensteiner

    R. Pallierer, M. Horauer, M Zauner, A. Steininger, E. Armengaud, F Rothensteiner:
    "A Generic Tool for Systematic Tests in Embedded Automotive Communication Systems";
    in: "Embedded World 2005", unbekannt, 2005.

    Zusätzliche Informationen

  9. Autor/innen: Adrian Prantl, E185 - 1; Jens Knoop, E185 - 1; Raimund Kirner, E182 - 1; Albrecht Kadlec, E182 - 1; Markus Schordan
    Andere beteiligte Person: Niklas Holsti

    A. Prantl, J. Knoop, R. Kirner, A. Kadlec, M Schordan:
    "From Trusted Annotations to Verified Knowledge";
    in: "Worst-Case Execution Time Analysis", N. Holsti (Hrg.); herausgegeben von: Oesterreichische Computer Gesellschaft / Austrian Computer Society; Verlag Oesterreichische Computer Gesellschaft, Wien, 2009, ISBN: 978-3-85403-252-6, S. 39 - 49.

  10. Autor/innen: Adrian Prantl, E185 - 1; Jens Knoop, E185 - 1; Raimund Kirner, E182 - 1; Albrecht Kadlec, E182 - 1; Markus Schordan
    Andere beteiligte Person: Niklas Holsti

    A. Prantl, J. Knoop, R. Kirner, A. Kadlec, M Schordan:
    "From Trusted Annotations to Verified Knowledge";
    in: "Worst-Case Execution Time Analysis", N. Holsti (Hrg.); herausgegeben von: Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany; Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany, Dagstuhl, Deutschland, 2009, ISBN: 978-3-939897-14-9, Paper-Nr. 8, 11 S.

  11. Autor/innen: Adrian Prantl, E185 - 1; Jens Knoop, E185 - 1; Raimund Kirner, E182 - 1; Albrecht Kadlec, E182 - 1; Markus Schordan
    Andere beteiligte Personen: Michael Hanus; Fabian Reck

    A. Prantl, J. Knoop, R. Kirner, A. Kadlec, M Schordan:
    "Towards an Orchestrated Approach for Annotation Verification";
    in: "27. Workshop der GI-Fachgruppe "Programmiersprachen und Rechenkonzepte"", M. Hanus, F. Reck (Hrg.); Christian-Albrechts-Universität Kiel, Deutschland, Kiel, Bericht Nr. 1010, 2010, S. 71 - 85.

  12. Autor/innen: Markus Proske, E182 - 2; Christian Trödhandl, E182 - 1

    M. Proske, C. Trödhandl:
    "Anytime, Everywhere - Approaches to Distance Labs in Embedded Systems Education - Extended Abstract";
    in: "Proceedings of ICTTA 2006", IEEE, 2006, S. 205 - 206.


Vorträge und Posterpräsentationen (mit Tagungsband-Eintrag)


  1. Autor/innen: Houssam Abbas; Alena Rodionova, E182 - 1; Ezio Bartocci, E182 - 1; Scott A. Smolka, Stony Brook U; Radu Grosu, E182 - 1

    H. Abbas, A. Rodionova, E. Bartocci, S. Smolka, R. Grosu:
    "Quantitative Regular Expressions for Arrhythmia Detection Algorithms";
    Vortrag: CMSB 2017: the 15th International Conference on Computational Methods in Systems Biology, Darmstadt, Germany; 27.09.2017 - 29.09.2017; in: "Proc. of CMSB 2017: the 15th International Conference on Computational Methods in Systems Biology", Springer, 10545 (2017), S. 23 - 39.

  2. Autor/in: Astrit Ademaj, E182 - 1

    A. Ademaj:
    "A Methodology for Dependability Evaluation of the Time-Triggered Architecture Using Software Implemented Fault Injection";
    Vortrag: European Dependable Computing Conference, Tolouse, France; 23.10.2002 - 25.10.2002; in: "Proceedings of the 4th European Dependable Computing Conference", (2002), S. 172 - 190.

    Zusätzliche Informationen

  3. Autor/in: Astrit Ademaj, E182 - 1

    A. Ademaj:
    "Achieving Fail Silence in the Time-Triggered Architecture";
    Vortrag: 6th IEEE International Workshop on Design and diagnostics of Electronics Circuits and Systems (DDECS'03), Poznan, Poland; 14.04.2003 - 16.04.2003; in: "Proceedings of the 6th IEEE Int. Workshop on Design and Diagnostics of Electronics Circuits and Systems (DDECS'03)", (2003), S. 165 - 170.

  4. Autor/in: Astrit Ademaj, E182 - 1

    A. Ademaj:
    "Slightly-Off-Specification Failures in the Time-Triggered Architecture";
    Vortrag: IEEE International Workshop on High Level Design Validation and Test, Cannes, France; 26.10.2002 - 28.10.2002; in: "Proceedings of the Seventh Annual IEEE International Workshop on High Level Design Validation and Test ", (2002), S. 7 - 12.

    Zusätzliche Informationen

  5. Autor/innen: Astrit Ademaj, E182 - 1; Günther Bauer, E182 - 1; Hakan Sivencrona; Jan Torin

    A. Ademaj, G. Bauer, H. Sivencrona, J. Torin:
    "Evaluation of Fault Handling of the Time-Triggered Architecture with Bus and Star Topology";
    Vortrag: IEEE International Conference on Dependable Systems and Networks, San Francisco, USA; 22.06.2003 - 25.06.2003; in: "Proceedings of the IEEE International Conference on Dependable Systems and Networks", (2003), S. 123 - 132.

  6. Autor/innen: Astrit Ademaj, E182 - 1; Petr Grillinger, E182 - 1; Jan Hlavicka

    A. Ademaj, P. Grillinger, J. Hlavicka:
    "Fault Tolerance Evaluation Using two Software Based Fault Injection Methods";
    Vortrag: International On-Line testing Workshop, France; 01.07.2002; in: "Proceedings of the International On-Line testing Workshop", (2002).

  7. Autor/innen: Astrit Ademaj, E182 - 1; Alexander Hanzlik, E182 - 1; Hermann Kopetz, E182 - 1

    A. Ademaj, A. Hanzlik, H. Kopetz:
    "Tolerating Arbitrary Failures in a Master-Slave Clock-Rate Correction Mechanism for Time-Triggered Fault-Tolerant Distributed Systems with Atomic Broadcast";
    Vortrag: International Conference on Real-Time and Network Systems (RTNS), Nancy, Frankreich; 29.03.2007 - 30.03.2007; in: "Proceedings of the 15th International Conference on Real-Time and Network Systems (RTNS'07)", Institut National Polytechnique de Lorraine, Nancy, Frankreich (2007), ISBN: 2-905267-53-4; S. 215 - 224.

    Zusätzliche Informationen

  8. Autor/innen: Astrit Ademaj, E182 - 1; Hermann Kopetz, E182 - 1

    A. Ademaj, H. Kopetz:
    "Time-Triggered Ethernet and IEEE 1588 Clock Synchronization";
    Vortrag: 2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication, Vienna; 01.10.2007 - 03.10.2007; in: "ISPCS 2007 Proceedings", (2007), ISBN: 1-4244-1064-9; Paper-Nr. 07 (Session 2/2), 3 S.

    Zusätzliche Informationen

  9. Autor/innen: Astrit Ademaj, E182 - 1; Hermann Kopetz, E182 - 1; Petr Grillinger, E182 - 1; Klaus Steinhammer, E182 - 1; Manfred Prammer

    A. Ademaj, H. Kopetz, P. Grillinger, K. Steinhammer, M. Prammer:
    "Integration of Predictable and Flexible In-Vehicle Communication using Time-Triggered Ethernet";
    Vortrag: SAE World Congress, Detroit, USA; 03.04.2006 - 06.04.2006; in: "SAE Worl Congress", SAE International, (2006), ISBN: 0-7680-1763-7.

    Zusätzliche Informationen

  10. Autor/innen: Astrit Ademaj, E182 - 1; Idriz Smaili, E182

    A. Ademaj, I. Smaili:
    "Setting Break-Points in Distributed Time-Triggered Architecture";
    Vortrag: IEEE International Workshop on High Level Design Validation and Test, Cannes, France; 01.10.2002; in: "Proceedings of the 7th Annual IEEE International Workshop on High Level Design Validation and Test", (2002).

  11. Autor/innen: Astrit Ademaj, E182 - 1; Klaus Steinhammer, E182 - 1; Petr Grillinger, E182 - 1; Hermann Kopetz, E182 - 1; Alexander Hanzlik, E182 - 1

    A. Ademaj, K. Steinhammer, P. Grillinger, H. Kopetz, A. Hanzlik:
    "Fault-Tolerant Time-Triggered Ethernet Configuration with Star Topology";
    Vortrag: 19th International Conference on Architecture of Computing systems (ARCS), Frankfurt/Main, Germany; 13.03.2006 - 16.03.2006; in: "19th International Conference on Architecture of Computing systems (ARCS'06), Proceedings of the", Springer-Verlag, (2006), ISBN: 3-540-32765-7.

    Zusätzliche Informationen

  12. Autor/in: Daniel Albeseder, E182 - 2

    D. Albeseder:
    "Evaluation of Message Delay Correlation in Distributed Systems";
    Vortrag: 3rd Workshop on Intelligent Solutions in Embedded Systems (WISES'05), Hamburg, Deutschland; 20.05.2005; in: "Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems", (2005), S. 139 - 150.

    Zusätzliche Informationen

  13. Autor/innen: Daniel Albeseder, E182 - 2; Josef Widder, E182 - 2

    D. Albeseder, J. Widder:
    "Simulating Distributed Real-Time Systems";
    Poster: Junior Scientist Conference, Wien; 19.04.2006 - 21.04.2006; in: "Junior Scientist Conference 2006", (2006), S. 83 - 84.

    Zusätzliche Informationen

  14. Autor/innen: K. Ambrosch; Martin Humenberger; Wilfried Kubinger; Andreas Steininger, E182 - 2

    K. Ambrosch, M. Humenberger, W. Kubinger, A. Steininger:
    "Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras";
    Vortrag: IEEE Conference on Computer Vision and Pattern Recognition, 2008. CVPR '08, Anchorage, Alaska, USA; 23.06.2008 - 28.06.2008; in: "CVPR Workshops 2008. IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, 2008.", (2008), ISBN: 978-1-4244-2339-2; S. 1 - 8.

    Zusätzliche Informationen

  15. Autor/innen: K. Ambrosch; Martin Humenberger; Wilfried Kubinger; Andreas Steininger, E182 - 2

    K. Ambrosch, M. Humenberger, W. Kubinger, A. Steininger:
    "Hardware Implementation of an SAD based stereo vision algorithm";
    Vortrag: Third IEEE Workshop on Embedded Computer Vision, Minneapolis; 23.06.2007; in: "Proceedings of Third IEEE Workshop on Embedded Computer Vision", (2007).

    Zusätzliche Informationen

  16. Autor/innen: Emmanuelle Anceaume; Carole Delporte-Gallet; Hugues Fauconnier; Michael Hurfin; Josef Widder, E182 - 2

    E. Anceaume, C. Delporte-Gallet, H. Fauconnier, M. Hurfin, J. Widder:
    "Clock Synchronization in the Byzantine-Recovery Failure Model";
    Vortrag: International Conference On Principles Of Distributed Systems (OPODIS), Guadeloupe; 17.12.2007 - 20.12.2007; in: "International Conference On Principles Of DIstributed System", (2007), S. 90 - 104.

    Zusätzliche Informationen

  17. Autor/innen: Christoph Angerer, E389; Ondrej Cevan; Loris Fauster; Yilin Huang; Benedikt Huber; Voin Legourski, E182 - 2; Simon Pirker; Thomas Polzer, E182 - 2; Daniel Reichhard; David Rigler; Alexandra Schuster; Bernhard Weirich; Peter Tummeltshammer, E182 - 2; Martin Delvai, E182 - 2

    C. Angerer, O. Cevan, L. Fauster, Y. Huang, B. Huber, V. Legourski, S. Pirker, T. Polzer, D. Reichhard, D. Rigler, A. Schuster, B. Weirich, P Tummeltshammer, M. Delvai:
    "Exploring Hardware Software Partitioning on the Example of a Face Recognition System";
    Poster: Austrochip, Graz; 11.10.2007; in: "Austrochip - Workshop on Microelectronics", (2007), ISBN: 978-3-902465-87-0; S. 121 - 127.

    Zusätzliche Informationen

  18. Autor/innen: Lorena Anghel, TIMA Labs Grenoble; Savulimedu Veeravall Varadan, E182 - 2; Dan Alexandrescu, IROC Technologies; Andreas Steininger, E182 - 2; Kerstin Schneider, E354; E. Costenaro, IROC Technologies

    L. Anghel, S. Varadan, D. Alexandrescu, A. Steininger, K. Schneider, E. Costenaro:
    "Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum";
    Vortrag: 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10), Stanford University, USA; 01.04.2014 - 02.04.2014; in: "Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10)", (2014), 6 S.

    Zusätzliche Informationen

  19. Autor/innen: Islam Ariful, Stony Brook U; Tushar Deshpande; Abhishek Murthy, Stony Brook U; Ezio Bartocci, E182 - 1; Scott A. Smolka, Stony Brook U; Scott D. Stoller, Stony Brook U; Radu Grosu, E182 - 1

    I. Ariful, T. Deshpande, A. Murthy, E. Bartocci, S. Smolka, S. Stoller, R. Grosu:
    "Tracking Action Potentials of Nonlinear Excitable Cells using Model Predictive Control";
    Vortrag: Sixth International Conference on Bioinformatics, Biocomputational Systems and Biotechnologies (BIOTECHNO), Chamonix, France; 20.04.2014 - 24.04.2014; in: "Proc. of BIOTECHNO 2014: The Sixth International Conference on Bioinformatics, Biocomputational Systems and Biotechnologies", IARIA, (2014), ISBN: 978-1-61208-335-3; S. 52 - 58.

  20. Autor/in: Eric Armengaud, E182 - 2

    E. Armengaud:
    "Experimental Evaluation of the FlexRay Clock Synchronization Service";
    Vortrag: 20. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Wien; 24.02.2008 - 26.02.2008; in: "20. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (2008), S. 85 - 89.

    Zusätzliche Informationen

  21. Autor/in: Eric Armengaud, E182 - 2

    E. Armengaud:
    "ExTraCT: A New Approach for the Transparent Test of Time-Triggered Communication Systems";
    Vortrag: 18. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Titisee; 12.03.2006 - 14.03.2006; in: "18. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (2006).

    Zusätzliche Informationen

  22. Autor/in: Eric Armengaud, E182 - 2

    E. Armengaud:
    "Low Level Bus Traffic Replay for the Test of Time-Triggered Communication Systems";
    Poster: 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS06), Prag; 18.04.2006 - 21.04.2006; in: "9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems", (2006), S. 155 - 156.

    Zusätzliche Informationen

  23. Autor/innen: Eric Armengaud, E182 - 2; Wolfgang Forster, E184 - 1

    E. Armengaud, W. Forster:
    "A Novel Interconnection Approach for Globally Asynchronous Locally Synchronous Circuits";
    Poster: Austrochip, Graz; 11.10.2007; in: "Austrochip - Workshop on Microelectronics", (2007), S. 107 - 113.

    Zusätzliche Informationen

  24. Autor/innen: Eric Armengaud, E182 - 2; Matthias Függer, E182 - 2; Andreas Steininger, E182 - 2

    E. Armengaud, M Függer, A. Steininger:
    "Safe deterministic replay for stimulating the clock synchronization algorithm in time-triggered systems";
    Vortrag: WFCS, Dresden, Germany; 20.05.2008 - 23.05.2008; in: "IEEE International Workshop on Factory Communication Systems, 2008. WFCS 2008.", (2008), ISBN: 978-1-4244-2349-1; S. 277 - 286.

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  25. Autor/innen: Eric Armengaud, E182 - 2; Florian Rothensteiner; Andreas Steininger, E182 - 2; Martin Horauer

    E. Armengaud, F Rothensteiner, A. Steininger, M. Horauer:
    "A Flexible Hardware Architecture for Fast Access on Large Non-Volatile Memories";
    Vortrag: IEEE International Workshop on Desgin & Diagnostic of Electronic Circuits and Systems, Sopron; 13.04.2005 - 16.04.2005; in: "Proceedings of IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS) 2005", (2005), S. 113 - 120.

    Zusätzliche Informationen

  26. Autor/innen: Eric Armengaud, E182 - 2; Andreas Steininger, E182 - 2

    E. Armengaud, A. Steininger:
    "A Remote and Transparent Approach for the Test and Diagnosis of Automotive Networks";
    Poster: Junior Scientist Conference, Wien; 19.04.2006 - 21.04.2006; in: "Junior Scientist Conference 2006", (2006).

    Zusätzliche Informationen

  27. Autor/innen: Eric Armengaud, E182 - 2; Andreas Steininger, E182 - 2

    E. Armengaud, A. Steininger:
    "Automatic Parameter Identification in FlexRay Based Automotive Communication Networks";
    Vortrag: IEEE International Conference on Emerging Technologies and Factory Automation, Prag; 20.09.2006 - 22.09.2006; in: "11th IEEE International Conference on Emerging Technologies and Factory Automation", (2006), S. 897 - 904.

    Zusätzliche Informationen

  28. Autor/innen: Eric Armengaud, E182 - 2; Andreas Steininger, E182 - 2

    E. Armengaud, A. Steininger:
    "Pushing the Limits of Remote Online Diagnosis in FlexRay Networks";
    Vortrag: IEEE International Workshop on Factory Communication Systems, Torino; 27.06.2006 - 30.06.2006; in: "6th IEEE International Workshop on Factory Communication Systems", (2006).

    Zusätzliche Informationen

  29. Autor/innen: Eric Armengaud, E182 - 2; Andreas Steininger, E182 - 2

    E. Armengaud, A. Steininger:
    "Remote Measurement of Local Oscillator Drifts in FlexRay Networks";
    Vortrag: DATE 2009 (Design, Automation and Test in Europe), Nice, France; 20.04.2009 - 24.04.2009; in: "DATE09", Springer, (2009), ISBN: 9783981080155; S. 1082 - 1087.

    Zusätzliche Informationen

  30. Autor/innen: Eric Armengaud, E182 - 2; Andreas Steininger, E182 - 2; Alexander Hanzlik, E182 - 1

    E. Armengaud, A. Steininger, A. Hanzlik:
    "The Effect of Quartz Drift on Convergence-Average based Clock Synchronization";
    Vortrag: IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), Patras; 25.09.2007 - 28.09.2007; in: "Proceedings of the 12th IEEE Conference on Emerging Technologies and Factory Automation", (2007), S. 1123 - 1130.

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  31. Autor/innen: Eric Armengaud, E182 - 2; Andreas Steininger, E182 - 2; Martin Horauer

    E. Armengaud, A. Steininger, M. Horauer:
    "A Method for Bit Level Test and Diagnosis of Communication Services";
    Vortrag: IEEE International Workshop on Desgin & Diagnostic of Electronic Circuits and Systems, Sopron; 13.04.2005 - 16.04.2005; in: "Proceedings of IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS) 2005", (2005), S. 69 - 74.

    Zusätzliche Informationen

  32. Autor/innen: Eric Armengaud, E182 - 2; Andreas Steininger, E182 - 2; Martin Horauer

    E. Armengaud, A. Steininger, M. Horauer:
    "An Efficient Test and Diagnosis Environment for Communication Controllers";
    Vortrag: Austrochip, Wien; 06.10.2005; in: "Austrochip 2005", ???, (2005).

    Zusätzliche Informationen

  33. Autor/innen: Eric Armengaud, E182 - 2; Andreas Steininger, E182 - 2; Martin Horauer

    E. Armengaud, A. Steininger, M. Horauer:
    "Efficient Stimulus Genereation for Remote Testing of Distributed Systems - The Flexray Example";
    Vortrag: ETFA, Catania, Italy; 19.09.2005 - 22.09.2005; in: "Proceedings of the 10th IEEE Internationla Conference on Emerging Technologies and Factory Automation", IEEE, I (2005), S. 763 - 770.

    Zusätzliche Informationen

  34. Autor/innen: Eric Armengaud, E182 - 2; Andreas Steininger, E182 - 2; Martin Horauer; Roman Pallierer, E182 - 1

    E. Armengaud, A. Steininger, M. Horauer, R. Pallierer:
    "A Layer Model for the Systematic Test of Time-Triggered Automotive Communication Systems";
    Vortrag: IEEE International Workshop on Factory Communication Systems, Vienna,Austria; 22.09.2004 - 24.09.2004; in: "IEEE Workshop on Factory Communication Systems (WFCS 04)", IEEE Catalog Number 04TH8777 (2004), ISBN: 0-7803-8734-1; S. 275 - 283.

    Zusätzliche Informationen

  35. Autor/innen: Eric Armengaud, E182 - 2; Andreas Steininger, E182 - 2; Martin Horauer; Roman Pallierer, E182 - 1

    E. Armengaud, A. Steininger, M. Horauer, R. Pallierer:
    "Design Trade-offs for Systematic Tests of Embedded Communication Systems";
    Vortrag: IEEE International Conference on Dependable Systems and Networks, Florence, Italy; 28.07.2004 - 01.08.2004; in: "International Conference on Dependable Systems and Networks (DSN 2004)", (2004), S. 118 - 119.

    Zusätzliche Informationen

  36. Autor/innen: Eric Armengaud, E182 - 2; Andreas Steininger, E182 - 2; Martin Horauer; Roman Pallierer, E182 - 1; Hannes Friedl

    E. Armengaud, A. Steininger, M. Horauer, R. Pallierer, H. Friedl:
    "A Monitoring Concept for an Automotive Distributed Network - The FlexRay Example";
    Vortrag: 7th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2004), Stara Lesna, Slovakia; 18.04.2004 - 21.04.2004; in: "Proceedings of the 7th Workshop on Design and Diognostics of Electronic Circuits and Systems", (2004), ISBN: 80-969117-9-1; S. 173 - 178.

    Zusätzliche Informationen

  37. Autor/innen: Sebastian Arming, E184 - 2; Ezio Bartocci, E182 - 1; Ana Sokolova, Universität Salzburg

    S. Arming, E. Bartocci, A. Sokolova:
    "SEA-PARAM: Exploring Schedulers in Parametric MDPs";
    Vortrag: QAPL 2017: the 15 International Workshop on Quantitative Aspects of Programming Languages and Systems, Uppsala, Sweden; 23.04.2017; in: "Proc. of QAPL 2017: the 15 International Workshop on Quantitative Aspects of Programming Languages and Systems", EPCTS, 250 (2017), S. 25 - 38.

  38. Autor/in: Pavel Atanassov, E182 - 1

    P. Atanassov:
    "Estimating the Delay Caused by DRAM Refreshes on the Execution Time of Real-Time Tasks";
    Vortrag: Specialized Informatics Congress, Gesellschaft für Informatik e.V., Bad Schussenried, Germany; 27.10.2000 - 28.10.2000; in: "Proceedings of the Informatiktage 2000, Specialized Informatics Congress, Gesellschaft für Informatik e.V.", (2000), S. #.

    Zusätzliche Informationen

  39. Autor/innen: Pavel Atanassov, E182 - 1; Peter Puschner, E182 - 1

    P. Atanassov, P. Puschner:
    "Impact of DRAM Refresh on the Execution Time of Real-Time Tasks";
    Vortrag: International Workshop on Application of Reliable Computing and Communication (in conjunction with PRDC 2001), Seoul, Korea; 01.12.2001; in: "Proceedings of the International Workshop on Application of Reliable Computing and Communication (in conjunction with PRDC 2001)", (2001), S. 29 - 34.

    Zusätzliche Informationen

  40. Autor/innen: Pavel Atanassov, E182 - 1; Peter Puschner, E182 - 1; Raimund Kirner, E182 - 1

    P. Atanassov, P. Puschner, R. Kirner:
    "Using Real Hardware to Create an Accurate Timing Model for Execution-Time Analysis";
    Vortrag: IEEE Workshop on Real-Time Embedded Systems, London, United Kingdom; 03.12.2001; in: "Proceedings of the IEEE International Workshop on Real-Time Embeeded Systems (in conjunction with 22nd IEEE RTSS 2001)", (2001).

    Zusätzliche Informationen

  41. Autor/innen: Ebru Aydin Gol, Boston University; Ezio Bartocci, E182 - 1; Calin Belta, Boston University

    E. Aydin Gol, E. Bartocci, C. Belta:
    "A Formal Methods Approach to Pattern Synthesis in Reaction Diffusion Systems";
    Vortrag: 53rd IEEE Inter. Conference on Decision and Control (CDC), Los Angeles; 15.12.2014 - 17.12.2014; in: "Proc. of CDC 2014: the IEEE 53rd Annual Conference on Decision and Control", IEEE, (2014), ISBN: 978-1-4799-7746-8; S. 108 - 113.

  42. Autor/innen: Iban Ayestaran; Carlos Fernando Nicolas; Jon Perez; Asier Larrucea Ortube; Peter Puschner, E182 - 1

    I. Ayestaran, Carlos Nicolas, J. Perez, A. Ortube, P. Puschner:
    "A Novel Modeling Framework for Time-Triggered Safety-Critical Embedded Systems";
    Vortrag: Forum on specification & Design Languages (FDL), Munich, Germany; 14.10.2014 - 16.10.2014; in: "Proceedings of the Forum on Specification & Design Languages (FDL 2014)", (2014).

    Zusätzliche Informationen

  43. Autor/innen: Iban Ayestaran; Carlos Fernando Nicolas; Jon Perez; Asier Larrucea Ortube; Peter Puschner, E182 - 1

    I. Ayestaran, Carlos Nicolas, J. Perez, A. Ortube, P. Puschner:
    "A Simulated Fault Injection Framework for Time-Triggered Safety-Critical Embedded Systems";
    Vortrag: International Conference on Computer Safety, Reliability and Security (SAFECOMP), Florence, Italy; 10.09.2014 - 12.09.2014; in: "Computer Safety, Reliability and Security", Lecture Notes in Computer Science / Springer, Volume 8666 (2014), ISBN: 978-3-319-10506-2; S. 1 - 16.

    Zusätzliche Informationen

  44. Autor/innen: Iban Ayestaran; Carlos Fernando Nicolas; Jon Perez; Asier Larrucea Ortube; Peter Puschner, E182 - 1

    I. Ayestaran, Carlos Nicolas, J. Perez, A. Ortube, P. Puschner:
    "Modeling and Simulated Fault Injection for Time-Triggered Safety-Critical Embedded Systems";
    Vortrag: 17th IEEE International Symposium on Object/Component-Oriented Real-Time Distributed Computing (ISORC), Reno, Nevada, USA; 08.06.2014 - 12.06.2014; in: "Proceedings 17th IEEE Symposium on Object/Component/Service-oriented Real-time distributed Computing (ISORC)", IEEE, (2014), ISSN: 1555-0885; S. 180 - 187.

    Zusätzliche Informationen

  45. Autor/innen: Iban Ayestaran; Carlos Fernando Nicolas; Jon Perez; Peter Puschner, E182 - 1

    I. Ayestaran, Carlos Nicolas, J. Perez, P. Puschner:
    "Modeling Logical Execution Time Based Safety-Critical Embedded Systems in SystemC";
    Vortrag: The Third Mediterranean Conference on Embedded Computing (MECO), Budva, Montenegro; 15.06.2014 - 19.06.2014; in: "Proceedings 3rd Mediterranean Conference on Embedded Computing (MECO)", IEEE, (2014), ISBN: 978-1-4799-4827-7; S. 77 - 80.

    Zusätzliche Informationen

  46. Autor/innen: Marco Baldi; Ezio Bartocci, E182 - 1; Franco Chiaraluce; Alessandro Cucchiarelli; Linda Senigagliesi; Luca Spalazzi; Francesco Spegni, UnivPM

    M. Baldi, E. Bartocci, F. Chiaraluce, A. Cucchiarelli, L. Senigagliesi, L. Spalazzi, F. Spegni:
    "A Probabilistic Small Model Theorem to Assess Confidentiality of Dispersed Cloud Storage";
    Vortrag: QEST 2017: the 14th International Conference on Quantitative Evaluation of SysTems, Berlin, Germany; 05.09.2017 - 07.09.2017; in: "Proc. of QEST 2017: the 14th International Conference on Quantitative Evaluation of SysTems", Springer, 10503 (2017), ISBN: 978-3-319-66335-7; S. 123 - 139.

  47. Autor/in: Ezio Bartocci, E182 - 1

    E. Bartocci:
    "Sampling-based Decentralized Monitoring for Networked Embedded Systems";
    Vortrag: HAS 2013, Rome, Italy; 17.03.2013; in: "Proc. of HAS 2013: the Third International Workshop on Hybrid Autonomous Systems", Electronic Proceedings in Theoretical Computer Science, vol. 124 (2013), ISSN: 2075-2180; S. 85 - 99.

    Zusätzliche Informationen

  48. Autor/innen: Ezio Bartocci, E182 - 1; Borzoo Bonakdarpour; Ylies Falcone

    E. Bartocci, B. Bonakdarpour, Y. Falcone:
    "First International Competition of Software for Runtime Verification";
    Vortrag: 14th International Conference on Runtime Verification, Canada (eingeladen); 22.09.2014 - 25.09.2014; in: "Proc. of RV 2014: the 14th International Conference on Runtime Verification", (2014), S. 1 - 9.

  49. Autor/innen: Ezio Bartocci, E182 - 1; Luca Bortolussi, Univ. of Trieste; Tomas Brazdil; Dimitrios Milos; Guido Sanguinetti

    E. Bartocci, L. Bortolussi, T. Brazdil, D. Milos, G. Sanguinetti:
    "Policy learning for time-bounded reachability in Continuous-Time Markov Decision Processes via doubly-stochastic gradient ascent";
    Vortrag: Quantitative Evaluation of Systems - 13th International Conference, QEST 2016, Quebec City, QC, Canada, August 23-25, 2016, Proceedings, Quebec City, QC, Canada; 23.08.2016 - 25.08.2016; in: "Quantitative Evaluation of Systems - 13th International Conference, QEST 2016, Quebec City, QC, Canada, August 23-25, 2016, Proceedings", Springer International Publishing, 9826 (2016), ISBN: 978-3-319-43424-7; S. 244 - 259.

    Zusätzliche Informationen

  50. Autor/innen: Ezio Bartocci, E182 - 1; Luca Bortolussi, Univ. of Trieste; MIchele Loreti; Laura Nenzi, IMT Lucca

    E. Bartocci, L. Bortolussi, M. Loreti, L. Nenzi:
    "Monitoring Mobile and Spatially Distributed Cyber-Physical Systems";
    Vortrag: MEMOCODE 2017: the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, Vienna, Austria; 29.09.2017 - 02.10.2017; in: "Proc. of MEMOCODE 2017: the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design", ACM, (2017), S. 146 - 155.

  51. Autor/innen: Ezio Bartocci, E182 - 1; Luca Bortolussi, Univ. of Trieste; Dimitrios Milos; Laura Nenzi, IMT Lucca; Guido Sanguinetti

    E. Bartocci, L. Bortolussi, D. Milos, L. Nenzi, G. Sanguinetti:
    "Studying Emergent Behaviours in Morphogenesis using Signal Spatio-Temporal Logic";
    Vortrag: 4th International Workshop on Hybrid Systems Biology (HSB), Madrid; 04.09.2015 - 05.09.2015; in: "Proc. of HSB 15: the 4th International Workshop on Hybrid Systems Biology", LNCS / LNBI / Springer, vol. 9271 (2015), S. 1 - 17.

  52. Autor/innen: Ezio Bartocci, E182 - 1; Luca Bortolussi, Univ. of Trieste; Laura Nenzi, IMT Lucca

    E. Bartocci, L. Bortolussi, L. Nenzi:
    "A temporal logic approach to modular design of synthetic biological circuits";
    Vortrag: CMSB 2013: the 11th International Conference on Computational Methods in Systems Biology, Klosterneuburg, Austria; 23.09.2013 - 25.09.2013; in: "Proc. of CMSB 2013: the 11th International Conference on Computational Methods in Systems Biology", LNCS/Springer, vol. 8130 (2013), ISBN: 978-3-642-40707-9; S. 164 - 178.

    Zusätzliche Informationen

  53. Autor/innen: Ezio Bartocci, E182 - 1; Luca Bortolussi, Univ. of Trieste; Laura Nenzi, IMT Lucca; Guido Sanguinetti

    E. Bartocci, L. Bortolussi, L. Nenzi, G. Sanguinetti:
    "On the Robustness of Temporal Properties for Stochastic Models";
    Vortrag: HSB 2013: the 2nd International Workshop on Hybrid Systems and Biology, Taormina, Italy; 02.09.2013; in: "Proceedings of the Second International Workshop on Hybrid Systems and Biology", Electronic Proceedings on Theoretical Computer Science, vol. 125 (2013), ISSN: 2075-2180; S. 3 - 19.

    Zusätzliche Informationen

  54. Autor/innen: Ezio Bartocci, E182 - 1; Luca Bortolussi, Univ. of Trieste; Guido Sanguinetti

    E. Bartocci, L. Bortolussi, G. Sanguinetti:
    "Data-driven Statistical Learning of Temporal Properties";
    Vortrag: 12th International Conference on Formal Modeling and Analysis of Timed Systems (FORMATS), Florence, Italy; 08.09.2014 - 12.09.2014; in: "Proc. of FORMATS 2014: the 12th International Conference on Formal Modeling and Analysis of Timed Systems", LNCS/Springer, vol. 8711 (2014), ISBN: 978-3-319-10511-6; S. 23 - 37.

  55. Autor/innen: Ezio Bartocci, E182 - 1; Elizabeth Cherry, Rochester Inst.; James Glimm, Stony Brook U; Radu Grosu, E182 - 1; Scott A. Smolka, Stony Brook U

    E. Bartocci, E. Cherry, J. Glimm, R. Grosu, S. Smolka:
    "Toward real-time simulation of cardiac dynamics";
    Vortrag: CMSB 2011: the 9th ACM International Conference on Computational Methods in Systems Biology, Paris, France; 21.09.2011 - 23.09.2011; in: "Proc. of CMSB 2011: the 9th ACM International Conference on Computational Methods in Systems Biology", ACM, (2011), ISBN: 978-1-4503-0817-5; S. 103 - 112.

    Zusätzliche Informationen

  56. Autor/innen: Ezio Bartocci, E182 - 1; Richard DeFrancisco; Scott A. Smolka, Stony Brook U

    E. Bartocci, R. DeFrancisco, S. Smolka:
    "Towards a GPGPU-parallel SPIN model checker";
    Vortrag: 21th International SPIN Symposium on Model Checking of Software, San Jose, California; 21.07.2014 - 23.07.2014; in: "SPIN 2014: International SPIN Symposium on Model Checking of Software", ACM, (2014), ISBN: 978-1-4503-2452-6; S. 87 - 96.

  57. Autor/innen: Ezio Bartocci, E182 - 1; Ylies Falcone

    E. Bartocci, Y. Falcone:
    "Runtime Verification and Enforcement, the (Industrial) Application Perspective (Track Introduction)";
    Vortrag: Leveraging Applications of Formal Methods, Verification and Validation: Foundational Techniques - 7th International Symposium, ISoLA 2016, Imperial, Corfu, Greece, October 10-14, 2016, Proceedings, Part I, Corfú, Greece (eingeladen); 10.10.2016 - 14.10.2016; in: "Leveraging Applications of Formal Methods, Verification and Validation: Foundational Techniques - 7th International Symposium, ISoLA 2016, Imperial, Corfu, Greece, October 10-14, 2016, Proceedings, Part I", Springer International Publishing, 9952 (2016), ISBN: 978-3-319-47166-2; S. 333 - 338.

    Zusätzliche Informationen

  58. Autor/innen: Ezio Bartocci, E182 - 1; Sicun Gao; Scott A. Smolka, Stony Brook U

    E. Bartocci, S. Gao, S. Smolka:
    "Medical Cyber-Physical Systems - (Track Introduction)";
    Vortrag: 6th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation (ISoLA 2014), Corfu (eingeladen); 08.10.2014 - 11.10.2014; in: "Proc. of ISoLA: the 6th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation", (2014), S. 353 - 355.

  59. Autor/innen: Ezio Bartocci, E182 - 1; Radu Grosu, E182 - 1

    E. Bartocci, R. Grosu:
    "Monitoring with uncertainty";
    Hauptvortrag: HAS 2013, Rome, Italy (eingeladen); 17.03.2013; in: "Proc. of HAS 2013: the Third International Workshop on Hybrid Autonomous Systems", Electronic Proceedings in Theoretical Computer Science, vol. 124 (2013), ISSN: 2075-2180; 4 S.

    Zusätzliche Informationen

  60. Autor/innen: Ezio Bartocci, E182 - 1; Radu Grosu, E182 - 1; Atul Karmarkar, Stony Brook U; Scott A. Smolka, Stony Brook U; Scott D. Stoller, Stony Brook U; Justin Seyster, Stony Brook U

    E. Bartocci, R. Grosu, A. Karmarkar, S. Smolka, S. Stoller, J. Seyster:
    "Adaptive Runtime Verification";
    Vortrag: RV 2012: the 3rd International Conference on Runtime Verification, Istanbul; 25.09.2012 - 28.09.2012; in: "Proc. of RV 2012: the 3rd International Conference on Runtime Verification", LNCS / Springer, vol. 7687 (2012), ISSN: 0302-9743; S. 168 - 182.

    Zusätzliche Informationen

  61. Autor/innen: Ezio Bartocci, E182 - 1; Radu Grosu, E182 - 1; Panagiotis Katsaros; C.R. Ramakrishnan; Scott A. Smolka, Stony Brook U

    E. Bartocci, R. Grosu, P. Katsaros, C. Ramakrishnan, S. Smolka:
    "Model Repair for Probabilistic Systems";
    Vortrag: 17th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), Saarbrücken, Germany; 26.03.2011 - 03.04.2011; in: "Proc. of 17th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS)", LNCS / Springer, vol. 6605 (2011), ISBN: 978-3-642-19834-2; S. 326 - 340.

    Zusätzliche Informationen

  62. Autor/innen: Iain Bate; Guillem Bernat; Greg Murphy; Peter Puschner, E182 - 1

    I. Bate, G. Bernat, G. Murphy, P. Puschner:
    "Low-Level Analysis of a Portable Java Byte Code WCET Analysis Framework";
    Vortrag: International Conference on Real-Time Computing Systems and Applications, Cheju Island, South Korea; 12.12.2000 - 14.12.2000; in: "Proceedings of the 7th International conference on Real-Time Computing Systems and Applications", (2000), S. 39 - 48.

    Zusätzliche Informationen

  63. Autor/innen: Iain Bate; Guillem Bernat; Peter Puschner, E182 - 1

    I. Bate, G. Bernat, P. Puschner:
    "Java Virtual-Machine Support for Portable Worst-Case Execution-time Analysis";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Washington, DC, USA; 29.04.2002 - 01.05.2002; in: "Proceedings of the 5th IEEE International Symposium on Object-oriented Real-time distributed Computing", (2002), S. 83 - 90.

    Zusätzliche Informationen

  64. Autor/innen: Günther Bauer, E182 - 1; Thomas Frenning; Anna-Karin Jonsson; Hermann Kopetz, E182 - 1; Christopher Temple, E182 - 1

    G. Bauer, T. Frenning, A.K. Jonsson, H. Kopetz, C. Temple:
    "A Centralized Approach for Avoiding the Babbling-Idiot Failure in the time-Triggered Architecture";
    Vortrag: ICDSN, New York, USA; 01.06.2000; in: "Proceedings of the ICDSN 2000", (2000), S. #.

    Zusätzliche Informationen

  65. Autor/innen: Günther Bauer, E182 - 1; Hermann Kopetz, E182 - 1

    G. Bauer, H. Kopetz:
    "Transparent Redundancy in the Time-Triggered Architecture";
    Vortrag: International Conference on Communications in Computing, Las Vegas, USA; 26.06.2000 - 29.06.2000; in: "Proceedings of the International Conference on Communications in Computing", (2000), S. #.

    Zusätzliche Informationen

  66. Autor/innen: Günther Bauer, E182 - 1; Hermann Kopetz, E182 - 1; Peter Puschner, E182 - 1

    G. Bauer, H. Kopetz, P. Puschner:
    "Assumption Coverage under Different Failure Modes in the Time-Triggered Architecture";
    Vortrag: IEEE International Conference on Emerging Technologies and Factory Automation, Antibes Juan-les-pins, France; 15.10.2001 - 18.10.2001; in: "Proceedings of the 8th IEEE International Conference on Emerging Technologies and Factory Automation", (2001), S. 333 - 341.

    Zusätzliche Informationen

  67. Autor/innen: Günther Bauer, E182 - 1; Hermann Kopetz, E182 - 1; Wilfried Steiner, E182 - 1

    G. Bauer, H. Kopetz, W. Steiner:
    "Byzantine Fault Containment in TTP/C";
    Vortrag: International Workshop on Real-Time LANs in the Internet Age, Vienna, Austria; 18.06.2002; in: "Proceedings of the 1st International Workshop on Real-Time LANs in the Internet Age", (2002).

    Zusätzliche Informationen

  68. Autor/innen: Günther Bauer, E182 - 1; Hermann Kopetz, E182 - 1; Wilfried Steiner, E182 - 1

    G. Bauer, H. Kopetz, W. Steiner:
    "The Central Guardian Approach to Enforce Fault Isolation in the Time-Triggered Architecture";
    Vortrag: 6th International Symposium on Autonomous Decentralized Systems (ISADS 03), Pisa, Italy; 09.04.2003 - 11.04.2003; in: "Proceedings of the Sixth International Symposium on Autonomous Decentralized Systems (ISADS 03)", (2003), S. 37 - 44.

    Zusätzliche Informationen

  69. Autor/innen: Günther Bauer, E182 - 1; Michael Paulitsch, E182 - 1

    G. Bauer, M. Paulitsch:
    "An Investigation of Membership and Clique Avoidance in TTP/C";
    Vortrag: IEEE Symposium on Reliable Distributed Systems, Nürnberg, Germany; 16.10.2000 - 18.10.2000; in: "Proceedings of the 19th IEEE Symposium on Reliable Distributed Systems", (2000), S. #.

    Zusätzliche Informationen

  70. Autor/innen: Mohamed Ben Sassi, E182 - 1; Ezio Bartocci, E182 - 1; Sriram Sankaranarayanan

    M. Ben Sassi, E. Bartocci, S. Sankaranarayanan:
    "A Linear Programming-based iterative approach to Stabilizing Polynomial Dynamics";
    Vortrag: IFAC 2017: the 20th World Congress of the International Federation of Automatic Control, Toulouse, France; 09.07.2017 - 14.07.2017; in: "IFAC 2017: the 20th World Congress of the International Federation of Automatic Control", Elsevier, 50 (1) (2017), S. 10462 - 10469.

  71. Autor/in: Martin Biely, E182 - 2

    M. Biely:
    "An optimal Byzantine agreement algorithm with arbitrary node and link failures.";
    Vortrag: IASTED International Conference on Parallel and Distributed Computing Systems, Marina Del Rey, California, USA; 03.11.2003 - 05.11.2003; in: "Proc. 15th Annual IASTED International Conference on Parallel", (2003), S. 146 - 151.

  72. Autor/innen: Martin Biely, E182 - 2; Bernadette Charron-Bost; Antoine Gaillard; Martin Hutle, E182 - 2; Andre Schiper; Josef Widder, E182 - 2

    M. Biely, B. Charron-Bost, A. Gaillard, M. Hutle, A. Schiper, J. Widder:
    "Tolerating Corrupted Communication";
    Vortrag: ACM Symposium on Principles of Distributed Computing, Portland; 12.08.2007 - 15.08.2007; in: "26th ACM Symposium on Principles of Distributed Computing (PODC'07)", (2007), S. 244 - 253.

    Zusätzliche Informationen

  73. Autor/innen: Martin Biely, E182 - 2; Martin Hutle, EPFL

    M. Biely, M. Hutle:
    "Consensus When All Processes May Be Byzantine for Some Time";
    Vortrag: 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems (SSS 2009), Lyon; 03.11.2009 - 06.11.2009; in: "Stabilization, Safety, and Security of Distributed Systems", Lecture Notes in Conputer Science / Springer Verlag, 5873 (2009), ISBN: 978-3-642-05117-3; S. 120 - 132.

    Zusätzliche Informationen

  74. Autor/innen: Martin Biely, E182 - 2; Martin Hutle, E182 - 2; Lucia Draque Penso; Josef Widder, E182 - 2

    M. Biely, M. Hutle, L. Penso, J. Widder:
    "Relating Stabilizing Timing Assumptions to Stabilizing Failure Detectors Regarding Solvability and Efficiency";
    Vortrag: Ninth International Symposium on Stabilization, Safety, and Security of Distributed Systems (SSS 2007), Paris; 14.11.2007 - 16.11.2007; in: "stabilization", (2007).

    Zusätzliche Informationen

  75. Autor/innen: Martin Biely, E182 - 2; G´erard Le Lann; Ulrich Schmid, E182 - 2

    M. Biely, G. Le Lann, U. Schmid:
    "Proof-Based System Engineering Using a Virtual System Model";
    Vortrag: International Service Availability Symposium, Berlin, Deutschland; 25.04.2005 - 26.04.2005; in: "Service Availability", (2005), S. 164 - 179.

    Zusätzliche Informationen

  76. Autor/innen: Martin Biely, EPFL; Peter Robinson; Ulrich Schmid, E182 - 2

    M. Biely, P. Robinson, U. Schmid:
    "Agreement in Directed Dynamic Networks";
    Vortrag: 19th International Colloquium on Structural Information and Communication Complexity (SIROCCO'12), Reykjavik, Iceland; 30.06.2012 - 02.07.2012; in: "Proceedings 19th International Colloquium on Structural Information and Communication Complexity (SIROCCO'12)", (2012), S. 73 - 84.

    Zusätzliche Informationen

  77. Autor/innen: Martin Biely, E182 - 2; Peter Robinson; Ulrich Schmid, E182 - 2

    M. Biely, P. Robinson, U. Schmid:
    "Brief Announcement: Easy Impossibility Proofs for k-Set Agreement in Message Passing Systems";
    Vortrag: Proceedings of the 30th Annual ACM Symposium on Principles of Distributed Computing (PODC'11), San Jose; 06.06.2011 - 08.06.2011; in: "PODC'11", ACM, (2011), S. 227 - 228.

  78. Autor/innen: Martin Biely, EPFL; Peter Robinson; Ulrich Schmid, E182 - 2

    M. Biely, P. Robinson, U. Schmid:
    "Easy Impossibility Proofs for k-Set Agreement in Message Passing Systems";
    Vortrag: International Conference On Principles Of Distributed Systems (OPODIS), Toulouse; 12.12.2011 - 16.12.2011; in: "OPODIS'11", Springer Berlin / Heidelberg, (2011), S. 299 - 312.

    Zusätzliche Informationen

  79. Autor/innen: Martin Biely, EPFL; Peter Robinson; Ulrich Schmid, E182 - 2

    M. Biely, P. Robinson, U. Schmid:
    "Solving k-Set Agreement with Stable Skeleton Graphs";
    Vortrag: International Parallel and Distributed Processing Symposium (IPDPS), Anachorage, Alaska; 16.05.2011 - 20.05.2011; in: "IPDPS Workshops", (2011), ISBN: 978-1-61284-425-1; S. 1488 - 1495.

    Zusätzliche Informationen

  80. Autor/innen: Martin Biely, E182 - 2; Peter Robinson, E182 - 2; Ulrich Schmid, E182 - 2

    M. Biely, P. Robinson, U. Schmid:
    "Weak Synchrony Models and Failure Detectors for Message Passing (k-)Set Agreement";
    Vortrag: OPODIS 2009 (International Conference On Principles Of Distributed Systems), Nimes, France; 15.12.2009 - 18.12.2009; in: "LNCS Proceedings", Springer, 5923/2009 (2009), ISBN: 9783642108761; S. 285 - 299.

    Zusätzliche Informationen

  81. Autor/innen: Martin Biely, EPFL; Peter Robinson; Ulrich Schmid, E182 - 2; Manfred Schwarz, E182 - 2; Kyrill Winkler, E182 - 2

    M. Biely, P. Robinson, U. Schmid, M. Schwarz, K. Winkler:
    "Gracefully Degrading Consensus and k-Set Agreement in Directed Dynamic Networks";
    Vortrag: The international Conference on NETworked sYStems, Agadir, Marokko; 13.05.2015 - 15.05.2015; in: "NETYS2015", Springer LNCS, 9466 (2015), ISBN: 978-3-319-26849-1.

    Zusätzliche Informationen

  82. Autor/innen: Martin Biely, E182 - 2; Josef Widder, E182 - 2

    M. Biely, J. Widder:
    "Optimal Message-Driven Implementations of Omega with Mute Processes";
    Vortrag: 8th International Symposium on Stabilization, Safety, and Security of Distributed Systems, Dallas; 17.11.2006 - 19.11.2006; in: "Stabilization, Safety, and Security of Distributed Systems", (2006), S. 110 - 121.

    Zusätzliche Informationen

  83. Autor/innen: Walter Binder; Martin Schoeberl, E182 - 1; Philippe Moret; Alex Villazón

    W. Binder, M. Schoeberl, P. Moret, A. Villazón:
    "Cross-Profiling for Embedded Java Processors";
    Vortrag: Fifth International Conference on the Quantitative Evaluation of Systems, St. Malo, France; 14.09.2008 - 17.09.2008; in: "Fifth International Conference on the Quantitative Evaluation of Systems", IEEE Computer Society, (2008), ISBN: 978-0-7695-3360-5; S. 287 - 296.

    Zusätzliche Informationen

  84. Autor/innen: Walter Binder; Alex Villazón; Martin Schoeberl, E182 - 1; Philippe Moret

    W. Binder, A. Villazón, M. Schoeberl, P. Moret:
    "Cache-aware Cross-profiling for Java Processors";
    Vortrag: International Conference on Compilers, Architecture and Synthesis for Embedded Systems [CASES 07], Atlanta,Georgia, USA; 19.10.2008 - 24.10.2008; in: "Ebedded Systems Week", (2008), ISBN: 978-1-60558-471-3; 9 S.

    Zusätzliche Informationen

  85. Autor/innen: Michael Birner, E182 - 2; Thomas Handl, E182 - 2

    M. Birner, T. Handl:
    "ARROW - A Generic Hardware Fault Injection Tool for NoCs";
    Vortrag: DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece; 27.08.2009 - 29.08.2009; in: "12th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - Architectures, Methods and Tools - DSD 2009", IEEE Computer Society, (2009), ISBN: 978-0-7695-3782-5; S. 465 - 472.

    Zusätzliche Informationen

  86. Autor/innen: Sara Blanc; Astrit Ademaj, E182 - 1; Hakan Sivencrona; Pedro Gil; Jan Torin

    S. Blanc, A. Ademaj, H. Sivencrona, P. Gil, J. Torin:
    "Three Different Fault Injection Techniques Combined to Improve the Detection Efficiency for Time-Triggered Systems";
    Vortrag: IEEE International Workshop on Desgin & Diagnostic of Electronic Circuits and Systems, Brno, Czech Republic; 17.04.2002 - 19.04.2002; in: "Proceedings of the 5th IEEE International Workshop on Design & Diagnostic of Electronic Circuits and Systems", (2002).

    Zusätzliche Informationen

  87. Autor/innen: Paul Bogdan, USC; Partha Pratim Pande, WSU; Hussam Amrouch, KIT; Muhammad Shafique, E182 - 2; Jörg Henkel, KIT

    P. Bogdan, P. Pande, H. Amrouch, M. Shafique, J. Henkel:
    "Power and Thermal Management in Massive Multicore Chips: Theoretical Foundation meets Architectural Innovation and Resource Allocation";
    Hauptvortrag: International Conference on Compilers, Architecture and Synthesis for Embedded Systems [CASES 07], Pittsburgh, Pennsylvania, USA (eingeladen); 01.10.2016 - 07.10.2016; in: "CASES", ACM, (2016), ISBN: 978-1-4503-4482-1.

    Zusätzliche Informationen

  88. Autor/innen: Sergiy Bogomolov, Univ. Freiburg; Alexandre Donze, Univ. of California; Goran Frehse, Verimag; Radu Grosu, E182 - 1; Taylor T. Johnson; Hamed Ladan, Univ. Freiburg; Andreas Podelski, Univ. Freiburg; Martin Wehrle, Univ. Freiburg

    S. Bogomolov, D. Donze, G. Frehse, R. Grosu, T. Johnson, H. Ladan, A. Podelski, M. Wehrle:
    "Abstraction-Based Guided Search for Hybrid Systems";
    Vortrag: International SPIN Symposium on Model Checking of Software (SPIN), Stony Brook, NY, USA; 08.07.2013 - 09.07.2013; in: "SPIN", LNCS, Springer, 7976 (2013), S. 117 - 134.

    Zusätzliche Informationen

  89. Autor/innen: Sergiy Bogomolov, Univ. Freiburg; Goran Frehse, Verimag; Radu Grosu, E182 - 1; Hamed Ladan, Univ. Freiburg; Andreas Podelski, Univ. Freiburg

    S. Bogomolov, G. Frehse, R. Grosu, H. Ladan, A. Podelski:
    "A Box-Based Distance between Regions for Guiding the Reachability Analysis of SpaceEx";
    Vortrag: CAV'12, the 24th International Conference on Computer Aided Verification, Berkeley, California, USA; 07.07.2012 - 13.07.2012; in: "Proceedings of CAV'12, the 24th International Conference on Computer Aided Verification", LNCS / Springer, 7358 (2012), ISBN: 978-3-642-31423-0; S. 479 - 494.

    Zusätzliche Informationen

  90. Autor/innen: Sergiy Bogomolov, Univ. Freiburg; Christian Schilling; Ezio Bartocci, E182 - 1; Gregory Batt; Hui Kong; Radu Grosu, E182 - 1

    S. Bogomolov, C. Schilling, E. Bartocci, G. Batt, H. Kong, R. Grosu:
    "Abstraction-based Parameter Synthesis for Multiaffine Systems";
    Vortrag: the 11th Haifa Verification Conference (HVC), Haifa, Israel; 17.11.2015 - 19.11.2015; in: "Proc. of HVC 2015: the 11th Haifa Verification Conference", LNCS / Springer, 9434 (2015), ISBN: 978-3-319-26286-4; S. 19 - 35.

    Zusätzliche Informationen

  91. Autor/innen: Florian Brandner, E185 - 1; Tommy Thorn; Martin Schoeberl, E182 - 1

    F. Brandner, T. Thorn, M. Schoeberl:
    "Embedded JIT Compilation with CACAO on YARI";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Tokyo, Japan; 17.03.2009 - 20.03.2009; in: "12th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing", IEEE, (2009), S. 63 - 70.

    Zusätzliche Informationen

  92. Autor/innen: Stefan Bruckner; Rudolf Seemann; Wilfried Elmenreich, E182 - 1

    S. Bruckner, R. Seemann, W. Elmenreich:
    "Applying a Real-Time Interface to an Optical Tracking System";
    Vortrag: Euromicro International Conference, Vienna, Austria; 19.06.2002 - 21.06.2002; in: "Proceedings of the Work-in-Progress Session of the 14th Euromicro International Conference", (2002), S. 49 - 52.

    Zusätzliche Informationen

  93. Autor/innen: Sven Bünte, E182 - 1; Raimund Kirner, E182 - 1

    S. Bünte, R. Kirner:
    "The Acquaintance of Hardware Timing Effects: A Sine Qua Non to Validate Temporal Requirements in Embedded Real Time Systems";
    Poster: Junior Scientist Conference 2008, Wien; 16.11.2008 - 18.11.2008; in: "Proceedings of the Junior Scientist Conference 2008", (2008), ISBN: 978-3-200-01612-5; S. 115 - 116.

  94. Autor/innen: Sven Bünte, E182 - 1; Michael Tautschnig

    S. Bünte, M. Tautschnig:
    "A Benchmarking Suite for Measurement-Based WCET Analysis Tools";
    Vortrag: International Conference on Software Testing Verification and Validation Workshop, 2008. ICSTW '08. IEEE, Lillehammer, Norway; 09.04.2008 - 11.04.2008; in: "International Conference on Software Testing Verification and Validation Workshop, 2008. ICSTW '08. IEEE", IEEE Computer Society, (2008), ISBN: 978-0-7695-3388-9; S. 353 - 356.

    Zusätzliche Informationen

  95. Autor/innen: Sven Bünte, E182 - 1; Michael Zolda, E182 - 1; Raimund Kirner, E182 - 1

    S. Bünte, M. Zolda, R. Kirner:
    "Let's Get Less Optimistic In Measurement-Based Timing Analysis";
    Vortrag: 6th International Symposium on Industrial Embedded Systems (SIES'11), Västeras, Sweden; 15.06.2011 - 17.06.2011; in: "Proc. 6th International Symposium on Industrial Embedded Systems (SIES'11)", (2011), ISBN: 978-1-61284-818-1; S. 204 - 212.

    Zusätzliche Informationen

  96. Autor/innen: Sven Bünte, E182 - 1; Michael Zolda, E182 - 1; Michael Tautschnig, E184 - 4; Raimund Kirner

    S. Bünte, M. Zolda, M. Tautschnig, R. Kirner:
    "Improving the Confidence in Measurement-Based Timing Analysis";
    Vortrag: 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC 2011), Newport Beach, California, USA; 28.03.2011 - 31.03.2011; in: "2011 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC 2011)", IEEE, (2011), ISBN: 978-1-61284-433-6; S. 144 - 151.

    Zusätzliche Informationen

  97. Autor/innen: Sara Bufo, Univ. of Trieste; Ezio Bartocci, E182 - 1; Guido Sanguinetti; Massimo Borelli, Univ. of Trieste; Umberto Lucangelo, Univ. of Trieste; Luca Bortolussi, Univ. of Trieste

    S. Bufo, E. Bartocci, G. Sanguinetti, M. Borelli, U. Lucangelo, L. Bortolussi:
    "Temporal Logic based Monitoring of Assisted Ventilaion in Intensive Care Patients";
    Vortrag: 6th International Symposium On Leveraging Applications of Formal Methods, Corfu', Greece (eingeladen); 08.10.2014 - 11.10.2014; in: "Proc. of ISoLA: 6th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation", (2014), S. 391 - 403.

  98. Autor/innen: Bernadette Charron-Bost; Shlomi Dolev; Jo Ebergen; Ulrich Schmid, E182 - 2

    B. Charron-Bost, S. Dolev, J. Ebergen, U. Schmid:
    "Fault Tolerant Distribiuted Algorithms and VLSI - An Appetizer";
    Vortrag: Dagstuhl Seminar 08371 : Fault-Tolerant Distributed Algorithms on VLSI Chips, Dagstuhl, Germany (eingeladen); 07.09.2009 - 10.09.2009; in: "Fault-Tolerant Distributed Algorithms on VLSI Chips", Leibniz Zentrum Informatik, 08371 (2009), ISSN: 1862-4405; S. ?.

    Zusätzliche Informationen

  99. Autor/innen: Bernadette Charron-Bost; Matthias Függer, E182 - 2; Thomas Nowak

    B. Charron-Bost, M Függer, T. Nowak:
    "Fast, Robust, Quantizable Approximate Consensus";
    Vortrag: International Colloquium on Automata, Languages and Programming (ICALP), Rome, Italy; 12.07.2016 - 15.07.2016; in: "Proceedings 43rd International Colloquium on Automata, Languages, and Programming (ICALP'16)", Leibniz International Proceedings in Informatics (LIPIcs), (2016), ISBN: 978-3-95977-013-2; S. 1 - 14.

    Zusätzliche Informationen

  100. Autor/innen: Bernadette Charron-Bost; Matthias Függer, E182 - 2; Thomas Nowak

    B. Charron-Bost, M Függer, T. Nowak:
    "Transience Bounds for Distributed Algorithms";
    Vortrag: 11th International Conference on Formal Modeling and Analysis of Timed Systems (FORMATS 2013), Buenos Aires, Argentina; 29.08.2013 - 31.08.2013; in: "Formal Modeling and Analysis of Timed Systems", Lecture Notes in Computer Science, 8053 (2013), ISBN: 978-3-642-40228-9; S. 77 - 90.

  101. Autor/innen: Bernadette Charron-Bost; Matthias Függer, E182 - 2; Jennifer Welch, Texas A&M Univer; Josef Widder

    B. Charron-Bost, M Függer, L. Welch, J. Widder:
    "Brief announcement: full reversal routing as a linear dynamical system";
    Vortrag: SPAA '11, San Jose, California, USA; 04.06.2011 - 06.06.2011; in: "Proceedings of the 23rd ACM symposium on Parallelism in algorithms and architectures", ACM, (2011), ISBN: 978-1-4503-0743-7; S. 129 - 130.

    Zusätzliche Informationen

  102. Autor/innen: Bernadette Charron-Bost; Matthias Függer, E182 - 2; Jennifer Welch, Texas A&M Univer; Josef Widder

    B. Charron-Bost, M Függer, L. Welch, J. Widder:
    "Full Reversal Routing as a Linear Dynamical System";
    Vortrag: Structural Information and Communication Complexity, Gdansk; 26.06.2011 - 29.06.2011; in: "Structural Information and Communication Complexity", Springer Berlin / Heidelberg, (2011), ISBN: 978-3-642-22211-5; S. 101 - 112.

    Zusätzliche Informationen

  103. Autor/innen: Bernadette Charron-Bost; Matthias Függer, E182 - 2; Jennifer Welch, Texas A&M Univer; Josef Widder

    B. Charron-Bost, M Függer, L. Welch, J. Widder:
    "Partial is Full";
    Vortrag: Structural Information and Communication Complexity, Gdansk; 26.06.2011 - 29.06.2011; in: "Structural Information and Communication Complexity", Springer Berlin / Heidelberg, (2011), ISBN: 978-3-642-22211-5; S. 113 - 124.

    Zusätzliche Informationen

  104. Autor/innen: Bernadette Charron-Bost; Antoine Gaillard; Jennifer Welch, Texas A&M Univer; Josef Widder, E182 - 2

    B. Charron-Bost, A. Gaillard, L. Welch, J. Widder:
    "Routing without Ordering";
    Vortrag: SPAA 2009 (Parallelism in Algorithms and Architectures), Calgary, Alberta, Canada; 11.08.2009 - 13.08.2009; in: "Proceedings of the Twenty-First Annual Symposium on Parallelism in Algorithms and Architectures", ACM, (2009), ISBN: 978-1-60558-606-9; S. 145 - 153.

    Zusätzliche Informationen

  105. Autor/innen: Bernadette Charron-Bost; Jennifer Welch, Texas A&M Univer; Josef Widder, E182 - 2

    B. Charron-Bost, L. Welch, J. Widder:
    "Link Reversal: How to Play Better to Work Less";
    Vortrag: ALGOSENSORS 2009 (5th International Workshop on Algorithmic Aspects of Wireless Sensor Networks), Rhodes, Greece; 10.07.2009 - 11.07.2009; in: "Algorithmic Aspects of Wireless Sensor Networks", Springer, 5304/2008 (2009), ISBN: 9783642054334; S. 88 - 110.

    Zusätzliche Informationen

  106. Autor/innen: Krishnendu Chatterjee; Alexander Kößler, E182 - 2; Ulrich Schmid, E182 - 2

    K. Chatterjee, A. Kößler, U. Schmid:
    "Automated Analysis of Real-Time Scheduling using Graph Games";
    Vortrag: ACM International Conference on Hybrid Systems: Computation and Control, Philadelphia, USA; 08.04.2013 - 11.04.2013; in: "Proceedings 16th ACM International Conference on Hybrid Systems: Computation and Control (HSCC'13)", ACM, (2013), S. 163 - 172.

  107. Autor/innen: Hyun Chul Chung; Peter Robinson, E182 - 2; Jennifer Welch, Texas A&M Univer

    H. Chung, P. Robinson, L. Welch:
    "Brief Announcement: Regional Consecutive Leader Election in Mobile Ad-Hoc Networks";
    Vortrag: ALGOSENSORS 2010 (6th International Workshop on Algorithmic Aspects of Wireless Sensor Networks), Bordeaux, France; 05.07.2010; in: "Algorithms for Sensor Systems - LNCS", Springer, 6451/2010 (2010), ISBN: 9783642169878; S. 90 - 91.

    Zusätzliche Informationen

  108. Autor/innen: Hyun Chul Chung; Peter Robinson, E182 - 2; Jennifer Welch, Texas A&M Univer

    H. Chung, P. Robinson, L. Welch:
    "Regional Consecutive Leader Election in Mobile Ad-Hoc Networks";
    Vortrag: ACM SIGACT/SIGMOBILE (International Workshop on FOUNDATIONS OF MOBILE COUMPUTING), Cambridge, Massachusetts, USA; 16.09.2010; in: "Proceedings of the 6th International Workshop on Foundations of Mobile Computing", ACM, (2010), ISBN: 9781450304139; S. 81 - 90.

    Zusätzliche Informationen

  109. Autor/innen: Bekim Cilku, E182 - 1; Alfons Crespo; Peter Puschner, E182 - 1; Javier Coronel; Peiro Salvador

    B. Cilku, A. Crespo, P. Puschner, J. Coronel, P. Salvador:
    "A TDMA-Based arbitration scheme for mixed-criticality multicore platforms";
    Vortrag: The first international conference on Event-based Control, Communication, and Signal Processing (EBCCSP), 2015, Krakow, Poland; 17.06.2015 - 19.06.2015; in: "Event-based Control, Communication, and Signal Processing (EBCCSP), 2015", IEEE, (2015), S. 1 - 6.

    Zusätzliche Informationen

  110. Autor/innen: Bekim Cilku, E182 - 1; Bernhard Frömel, E182 - 1; Peter Puschner, E182 - 1

    B. Cilku, B. Frömel, P. Puschner:
    "A Dual-Layer Bus Arbiter for Mixed-Criticality Systems with Hypervisors";
    Vortrag: 12th IEEE International Conference on Industrial Informatics, Porto Alegre, Brazil; 27.07.2014 - 30.07.2014; in: "Proc. of the 12th IEEE International Conference on Industrial Informatics", (2014), ISBN: 978-1-4799-4906-9; S. 147 - 151.

    Zusätzliche Informationen

  111. Autor/innen: Bekim Cilku, E182 - 1; Roland Kammerer, E182 - 1; Peter Puschner, E182 - 1

    B. Cilku, R. Kammerer, P. Puschner:
    "Aligning Single Path Loops to Reduce the Number of Capacity Cache Misses";
    Vortrag: 6th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems, Vancouver, Canada; 03.12.2013 - 06.12.2013; in: "Proceedings of the 34th IEEE Real-Time Systems Symposium, 6th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems", (2013).

    Zusätzliche Informationen

  112. Autor/innen: Bekim Cilku, E182 - 1; Daniel Prokesch, E182 - 1; Peter Puschner, E182 - 1

    B. Cilku, D. Prokesch, P. Puschner:
    "A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking";
    Vortrag: 11th International IEEE/IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems SEUS 2015, Auckland, New Zealand; 13.04.2015; in: "Proc. 18th IEEE International Symposium on Real-Time Computing (ISORC 2015) Workshops", IEEE, (2015), ISBN: 978-1-4673-7709-6; S. 74 - 79.

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  113. Autor/innen: Bekim Cilku, E182 - 1; Wolfgang Puffitsch, DTU; Daniel Prokesch, E182 - 1; Martin Schoeberl; Peter Puschner, E182 - 1

    B. Cilku, W. Puffitsch, D. Prokesch, M. Schoeberl, P. Puschner:
    "Improving Performance of Single-path Code Through a Time-predictable Memory Hierarchy";
    Vortrag: 20th IEEE International Symposium on Real-Time Computing (ISORC 2017), Toronto, Canada; 16.05.2017 - 18.05.2017; in: "Proc. 20th IEEE International Symposium on Real-Time Computing (ISORC 2017)", IEEE, (2017), ISBN: 978-1-5386-1574-4; S. 76 - 83.

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  114. Autor/innen: Bekim Cilku, E182 - 1; Peter Puschner, E182 - 1

    B. Cilku, P. Puschner:
    "Designing a Time-Predictable Memory Hierarchy for Single-Path Code";
    Vortrag: 7 th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems (CRTS14), Rome, Italy; 02.12.2014; in: "Designing a Time-Predictable Memory Hierarchy for Single-Path Code", (2014), S. 9 - 14.

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  115. Autor/innen: Bekim Cilku, E182 - 1; Peter Puschner, E182 - 1

    B. Cilku, P. Puschner:
    "Towards a Time-Predictable Hierarchical Memory Architecture - Prefetching Options to be Explored";
    Vortrag: Proc. 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW 2010), Carmona, Sevilla, Spain; 04.05.2010 - 07.05.2010; in: "Towards a Time-Predictable Hierarchical Memory Architecture - Prefetching Options to be Explored", (2010), S. 219 - 225.

    Zusätzliche Informationen

  116. Autor/innen: Bekim Cilku, E182 - 1; Peter Puschner, E182 - 1

    B. Cilku, P. Puschner:
    "Towards Temporal and Spatial Isolation in Memory Hierarchies for Mixed-Criticality Systems with Hypervisors";
    Vortrag: 1st Workshop on Real-Time Mixed Criticality Systems, Taipei, Taiwan; 21.08.2013; in: "Proceedings of the 19th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 1st workshop on Real-Time Mixed Criticality Systems", (2013).

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  117. Autor/innen: Bekim Cilku, E182 - 1; Peter Puschner, E182 - 1

    B. Cilku, P. Puschner:
    "Using a Local Prefetch Strategy to Obtain Temporal Time Predictability";
    Vortrag: 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW), Newport Beach, California, USA; 28.03.2011 - 31.03.2011; in: "Proc. 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW)", IEEE, (2011), ISBN: 978-1-4577-0303-4; S. 227 - 234.

    Zusätzliche Informationen

  118. Autor/innen: Bekim Cilku, E182 - 1; Peter Puschner, E182 - 1

    B. Cilku, P. Puschner et al.:
    "A Memory Arbitration Scheme for Mixed-Criticality Multicore Platforms";
    Vortrag: 2 nd International Workshop on Mixed Criticality Systems (WMC14), Rome, Italy; 02.12.2014; in: "Proceedings of the 2 nd International Workshop on Mixed Criticality Systems", (2014), S. 27 - 32.

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  119. Autor/innen: David De Andrés; Sara Blanc; Pedro Gil; Astrit Ademaj, E182 - 1; Klaus Steinhammer, E182 - 1

    D. De Andrés, S. Blanc, P. Gil, A. Ademaj, K. Steinhammer:
    "BUFI: Fault injector for communication buses";
    Vortrag: IEEE Conference on Dependable Systems and Networks (DSN), Philadelphia, PA, USA; 25.06.2006 - 28.06.2006; in: "IEEE Conference on Dependable Systems and Networks (DSN06), Proceedings", (2006).

    Zusätzliche Informationen

  120. Autor/innen: Philipp Degasperi, E182 - 1; Stefan Hepp, E185 - 1; Wolfgang Puffitsch, DTU; Martin Schöberl, DTU

    P. Degasperi, S Hepp, W. Puffitsch, M. Schöberl:
    "A Method Cache for Patmos";
    Vortrag: 17th IEEE International Symposium on Object/Component-Oriented Real-Time Distributed Computing (ISORC), Reno, Nevada, USA; 08.06.2014 - 12.06.2014; in: "Proc. of the 17th IEEE International Symposium on Object/Component-Oriented Real-Time Distributed Computing", (2014), ISSN: 1555-0885; S. 100 - 108.

    Zusätzliche Informationen

  121. Autor/innen: Martin Delvai, E182 - 2; Ulrike Eisenmann; Wilfried Elmenreich, E182 - 1

    M. Delvai, U. Eisenmann, W. Elmenreich:
    "Intelligent UART Module for Real-Time Applications";
    Vortrag: Workshop on Intelligent Solutions in Embedded Systems (WISES'03), Wien; 27.06.2003; in: "Proceedings of the First Workshop on Intelligent Solutions in Embedded Systems", (2003), S. 177 - 185.

  122. Autor/innen: Martin Delvai, E182 - 2; Ulrike Eisenmann; Wolfgang Huber, E182 - 2

    M. Delvai, U. Eisenmann, W. Huber:
    "Modular Construction System for Embedded Real-Time Applications";
    Poster: Austrochip, Wien; 04.10.2002; in: "Austrochip 2002", (2002), S. 103 - 109.

  123. Autor/innen: Martin Delvai, E182 - 2; Christian El Salloum; Andreas Steininger, E182 - 2

    M. Delvai, C. El Salloum, A. Steininger:
    "A Generic Real-time Debugger Architecture";
    Vortrag: World Multiconference on Systemics, cybernetics and Informatics, Orlando, Florida; 27.07.2003 - 30.07.2003; in: "The 7th World Multiconference on Systemics, Cybernetics and Informatics", (2003), S. 65 - 70.

  124. Autor/innen: Martin Delvai, E182 - 2; Gottfried Fuchs, E182 - 2

    M. Delvai, G. Fuchs:
    "LANCE: A 16 Bit Superscalar Processor";
    Vortrag: Austrochip, Linz; 03.10.2003; in: "Austrochip 2003", (2003), S. 87 - 90.

  125. Autor/innen: Martin Delvai, E182 - 2; Gottfried Fuchs, E182 - 2; Thomas Handl, E182 - 2; Wolfgang Huber, E182 - 2; Andreas Steininger, E182 - 2

    M. Delvai, G. Fuchs, T. Handl, W. Huber, A. Steininger:
    "Design of an Asynchronous Microprocessor with Four-State Logic";
    Vortrag: Austrochip, Wien; 06.10.2005; in: "Austrochip 2005", (2005), S. 105 - 112.

    Zusätzliche Informationen

  126. Autor/innen: Martin Delvai, E182 - 2; Wolfgang Huber, E182 - 2; Peter Puschner, E182 - 1; Andreas Steininger, E182 - 2

    M. Delvai, W. Huber, P. Puschner, A. Steininger:
    "Processor Support for Temporal Predictability - The SPEAR Design Example";
    Vortrag: 15th Euromicro Conference on Real-Time Systems, Porto, Portugal; 02.07.2003 - 04.07.2003; in: "Proceedings of the 15 Euromicro International Conference on Real-Time Systems", (2003), S. 169 - 176.

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  127. Autor/innen: Martin Delvai, E182 - 2; Wolfgang Huber, E182 - 2; Babak Rahbaran, E182 - 2; Andreas Steininger, E182 - 2

    M. Delvai, W. Huber, B. Rahbaran, A. Steininger:
    "An FPGA-Based Development Platform for the virtual Real-Time Processor Component SPEAR";
    Vortrag: IEEE Design and Diagnostics of Electronic Circuits and Systems (IEEE DDECS 2002), Brno, Czech Republic; 17.04.2002 - 19.04.2002; in: "Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop", (2002), S. 98 - 105.

    Zusätzliche Informationen

  128. Autor/innen: Martin Delvai, E182 - 2; Wolfgang Huber, E182 - 2; Babak Rahbaran, E182 - 2; Andreas Steininger, E182 - 2

    M. Delvai, W. Huber, B. Rahbaran, A. Steininger:
    "SPEAR-Design-Entscheidungen für den "Scalable Processor for Embeded Application in Real-Time Environment"";
    Vortrag: Austrochip, wien; 12.10.2001; in: "Die Österreichische Tagnung zum Themenbereich Mikroelektronik", (2001), S. 25 - 32.

    Zusätzliche Informationen

  129. Autor/innen: Martin Delvai, E182 - 2; Martin Jankela; Andreas Steininger, E182 - 2

    M. Delvai, M. Jankela, A. Steininger:
    "Towards Virtual Prototyping of Embedded Computer Systems";
    Poster: The 7th World Multiconference on Systemics, Cybernetics and Informatics, Orlando, Florida; 27.07.2003 - 30.07.2003; in: "Proceedings, Volume I, Information Systems, Technologies and Applications", (2003), S. 70 - 75.

  130. Autor/innen: Martin Delvai, E182 - 2; Thomas Panhofer

    M. Delvai, T. Panhofer:
    "SELF-HEALING CIRCUITS FOR SPACE-APPLICATIONS";
    Poster: 17th International Conference on Field Programmable Logic and Applications (FPL2007), Amsterdam; 27.08.2007 - 29.08.2007; in: "Proceedings of 17th INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS", (2007), ISBN: 1-4244-1060-6; S. 505 - 506.

  131. Autor/innen: Martin Delvai, E182 - 2; Andreas Steininger, E182 - 2

    M. Delvai, A. Steininger:
    "A Practical Comparison of Logic Design Styles";
    Vortrag: The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications, Orlando; 20.07.2006 - 23.07.2006; in: "The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications - Volume 3", (2006), S. 61 - 66.

    Zusätzliche Informationen

  132. Autor/innen: Martin Delvai, E182 - 2; Andreas Steininger, E182 - 2

    M. Delvai, A. Steininger:
    "Asynchronous Logic Design - from Concepts to Implementation";
    Vortrag: The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications, Orlando; 20.07.2006 - 23.07.2006; in: "The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications - Volume 1", (2006), S. 81 - 86.

    Zusätzliche Informationen

  133. Autor/innen: Martin Delvai, E182 - 2; Andreas Steininger, E182 - 2

    M. Delvai, A. Steininger:
    "Solving the Fundamental Problem of Digital Design -- A Systematic Review of Design Methods";
    Poster: 9th Euromicro Conference on Digital System Design, Dubrovnik; 30.08.2006 - 01.09.2006; in: "9th Euromicro Conference on Digital System Design - Architectures, Methods and Tools", (2006), S. 131 - 136.

    Zusätzliche Informationen

  134. Autor/innen: Martin Delvai, E182 - 2; Andreas Steininger, E182 - 2

    M. Delvai, A. Steininger:
    "Teaching Hardware Software Codesign to Software Engineers";
    Vortrag: 1st International Workshop on Reconfigurable Computing Education, Karlsruhe; 01.03.2006; in: "International Workshop on Reconfigurable Computing Education", (2006).

    Zusätzliche Informationen

  135. Autor/innen: Andreas Dielacher, E182 - 2; Matthias Függer, E182 - 2

    A. Dielacher, M Függer:
    "How to Speed-up Fault-tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining";
    Vortrag: PODC 2009 (Principles of Distribiuted Computing), Alberta, Canada (eingeladen); 10.08.2009 - 12.08.2009; in: "PODC'09", ACM, (2009), ISBN: 9781605583969; S. 276 - 277.

    Zusätzliche Informationen

  136. Autor/innen: Radu Dobrin; Gerhard Fohler; Peter Puschner, E182 - 1

    R Dobrin, G. Fohler, P. Puschner:
    "Translating Offline Schedules into Task Attributes for Fixed Priority Scheduling";
    Vortrag: IEEE Real-Time Systems Symposium, London, United Kingdom; 04.12.2001 - 06.12.2001; in: "Proceedings of the 22nd IEEE Real-Time Systems Symposium", (2001), S. 225 - 234.

    Zusätzliche Informationen

  137. Autor/innen: Danny Dolev; Matthias Függer, E182 - 2; Christoph Lenzen; Ulrich Schmid, E182 - 2

    D. Dolev, M Függer, C. Lenzen, U. Schmid:
    "Fault-Tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation [Extended Abstract]";
    Vortrag: Stabilization, Safety, and Security of Distributed Systems, Grenoble, France; 10.10.2011 - 12.10.2011; in: "Stabilization, Safety, and Security of Distributed Systems", Springer Berlin / Heidelberg, (2011), ISBN: 978-3642051173; S. 163 - 177.

    Zusätzliche Informationen

  138. Autor/innen: Danny Dolev; Christoph Lenzen; Matthias Függer, E182 - 2; Ulrich Schmid, E182 - 2; Martin Perner, E182 - 2

    D. Dolev, C. Lenzen, M Függer, U. Schmid, M. Perner:
    "HEX: Scaling Honeycombs is Easier than Scaling Clock Trees";
    Vortrag: SPAA '13, Montreal, Canada; 23.07.2013 - 25.07.2013; in: "Proceedings of the 25th ACM symposium on Parallelism in Algorithms and Architectures", ACM, (2013), ISBN: 978-1-4503-1572-2; S. 164 - 175.

    Zusätzliche Informationen

  139. Autor/innen: Alexandre Donze, Univ. of California; Oded Maler, Verimag; Ezio Bartocci, E182 - 1; Dejan Nickovic, AIT; Radu Grosu, E182 - 1; Scott A. Smolka, Stony Brook U

    D. Donze, O. Maler, E. Bartocci, D. Nickovic, R. Grosu, S. Smolka:
    "On Temporal Logic and Signal Processing";
    Vortrag: Automated Technology for Verification and Analysis (ATVA), Thiruvananthapuram, India; 03.10.2012 - 06.10.2012; in: "Proceedings of ATVA 2012, the 10th International Symposium on Automated Technology for Verification and Analysis", LNCS/Springer, vol. 7561 (2012), ISBN: 978-3-642-33385-9; S. 92 - 106.

    Zusätzliche Informationen

  140. Autor/innen: Dietmar Ebner, E185 - 1; Florian Brandner, E185 - 1; Bernhard Scholz; Andreas Krall, E185 - 1; Peter Wiedermann; Albrecht Kadlec, E182 - 1

    D. Ebner, F. Brandner, B. Scholz, A. Krall, P. Wiedermann, A. Kadlec:
    "Generalized instruction selection using SSA-graphs";
    Vortrag: ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, Tucson, Arizona, USA; 12.06.2008 - 13.06.2008; in: "Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems", ACM - Association for Computing Machinery, (2008), ISBN: 978-1-60558-104-0; S. 31 - 40.

    Zusätzliche Informationen

  141. Autor/innen: Stephen A. Edwards; Sungjun Kim; Edward A. Lee; Isaac Liu; Hiren D. Patel; Martin Schoeberl, E182 - 1

    S. Edwards, S. Kim, E. Lee, I. Liu, H. Patel, M. Schoeberl:
    "A Disruptive Computer Design Idea: Architectures with Repeatable Timing";
    Vortrag: 2009 IEEE International Conference on Computer Design, Resort at Squaw Creek, Lake Tahoe, California; 04.10.2009 - 07.10.2009; in: "2009 IEEE International Conference on Computer Design", IEEE, CFP09ICD (2009), ISBN: 978-1-4244-5028-2; S. 54 - 59.

    Zusätzliche Informationen

  142. Autor/innen: Christian El Salloum, E182 - 1; Martin Elshuber, E182 - 1; Oliver Höftberger, E182 - 1; Haris Isakovic, E182 - 1; Armin Wasicek, E182 - 1

    C. El Salloum, M. Elshuber, O. Höftberger, H. Isakovic, A. Wasicek:
    "The ACROSS MPSoC - A New Generation of Multi-Core Processors designed for Safety-Critical Embedded Systems";
    Vortrag: DSD 2012 (Euromicro Conference on Digital System Design), Cesme, Izmir, Turkey (eingeladen); 05.09.2012 - 08.09.2012; in: "2012 15th Euromicro Conference on Digital System Design (DSD 2012), Proceedings", IEEE Computer Society, (2012), ISBN: 978-1-4673-2498-4; S. 105 - 113.

    Zusätzliche Informationen

  143. Autor/innen: Christian El Salloum, E182 - 1; Roman Obermaisser, Universität Siegen; Bernhard Huber, E182 - 1; Hermann Kopetz, E182 - 1

    C. El Salloum, R. Obermaisser, B. Huber, H. Kopetz:
    "A Novel Naming Scheme for System-on-a-Chips Supporting Dynamic Resource Management";
    Vortrag: Seventh European Dependable Computing Conference (EDCC-7), Kaunas, Lithuania; 07.05.2008 - 09.05.2008; in: "Seventh European Dependable Computing Conference (EDCC-7)", IEEE Computer Society, (2008), ISBN: 978-0-7695-3138-0; S. 135 - 144.

    Zusätzliche Informationen

  144. Autor/innen: Christian El Salloum, E182 - 1; Roman Obermaisser, Universität Siegen; Bernhard Huber, E182 - 1; Hermann Kopetz, E182 - 1; Neeraj Suri

    C. El Salloum, R. Obermaisser, B. Huber, H. Kopetz, N. Suri:
    "Supporting Heterogeneous Applications in the DECOS Integrated Architecture";
    Vortrag: International DECOS Workshop, Vienna, Austria; 12.10.2006; in: "International DECOS Workshop", (2006).

    Zusätzliche Informationen

  145. Autor/innen: Christian El Salloum, E182 - 1; Roman Obermaisser, Universität Siegen; Bernhard Huber, E182 - 1; Harald Paulitsch, E182 - 1; Hermann Kopetz, E182 - 1

    C. El Salloum, R. Obermaisser, B. Huber, H. Paulitsch, H. Kopetz:
    "A time-triggered system-on-a-chip architecture with integrated support for diagnosis";
    Vortrag: Design, Automation and Test in Europe Conference (DATE'07), Nice, France; 16.04.2007 - 20.04.2007; in: "Workshop Digest, Diagnostic Services in Network-on-Chips", DATE'07, (2007), Paper-Nr. 3 (Seite 136f), 2 S.

    Zusätzliche Informationen

  146. Autor/innen: Christian El Salloum, E182 - 1; Andreas Steininger, E182 - 2; Peter Tummeltshammer, E182 - 2

    C. El Salloum, A. Steininger, P Tummeltshammer:
    "Recovery Mechanisms for Dual Core Architectures";
    Vortrag: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT ), Washington DC, USA; 04.10.2006 - 06.10.2006; in: "21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006, Proceedings", (2006), ISBN: 0-7695-2706-x; S. 380 - 388.

    Zusätzliche Informationen

  147. Autor/in: Wilfried Elmenreich, E182 - 1

    W. Elmenreich:
    "A Review on System Architectures for Sensor Fusion Applications";
    Vortrag: 5th IFIP Workshop on Software Technologies for Future Embedded & Ubiquitous Systems (SEUS 2007), Santorini, Greece; 07.05.2007 - 08.05.2007; in: "The 5th IFIP Workshop on Software Technologies for Future Embedded & Ubiquitous Systems", (2007), Paper-Nr. p7-5, 12 S.

    Zusätzliche Informationen

  148. Autor/in: Wilfried Elmenreich, E182 - 1

    W. Elmenreich:
    "Fault-Tolerant Certainty Grid";
    Vortrag: ICAR International Conference on Advanced Robotics, Coimbra, Portugal; 30.06.2003 - 03.07.2003; in: "Proceedings of the 11th International Conference on Advanced Robotics", 3 (2003), ISBN: 972-96889-8-2; S. 1576 - 1581.

    Zusätzliche Informationen

  149. Autor/in: Wilfried Elmenreich, E182 - 1

    W. Elmenreich:
    "Intelligent Methods for Embedded Systems";
    Vortrag: Workshop on Intelligent Solutions in Embedded Systems, Vienna, Austria; 27.06.2003; in: "Proceedings of the Workshop on Intelligent Solutions in Embedded Systems", (2003), S. 3 - 11.

    Zusätzliche Informationen

  150. Autor/innen: Wilfried Elmenreich, E182 - 1; Günther Bauer, E182 - 1; Hermann Kopetz, E182 - 1

    W. Elmenreich, G. Bauer, H. Kopetz:
    "The Time-Triggered Paradigm";
    Vortrag: Workshop on Time-Triggered and Real-Time Communication Systems, Manno, Switzerland (eingeladen); 02.12.2003; in: "Proccedings of the Workshop on Time-Triggered and Real-Time Communication Systems", (2003), 9 S.

    Zusätzliche Informationen

  151. Autor/innen: Wilfried Elmenreich, E182 - 1; Martin Delvai, E182 - 2

    W. Elmenreich, M. Delvai:
    "Time-Triggered Communication with UARTs";
    Vortrag: IEEE International Workshop on Factory Communication Systems, Västeraas; 28.08.2002 - 30.08.2002; in: "Proceedings of the 4th IEEE International Workshop on Factory Communication Systems", (2002), S. 97 - 104.

    Zusätzliche Informationen

  152. Autor/innen: Wilfried Elmenreich, E182 - 1; Wolfgang Haidinger, E182 - 1; Hermann Kopetz, E182 - 1

    W. Elmenreich, W. Haidinger, H. Kopetz:
    "Interface Design for Smart Transducers";
    Vortrag: IEEE Instrumentation and Measurement Technology Conference (IMTC), Budapest, Hungary; 21.05.2001 - 23.05.2001; in: "Proceedings of the IEEE Instrumentation and Measurement Technology Conference (IMTC)", Vol. 3 (2001), S. 1642 - 1647.

    Zusätzliche Informationen

  153. Autor/innen: Wilfried Elmenreich, E182 - 1; Wolfgang Haidinger, E182 - 1; Philipp Peti, E182 - 1; Lukas Schneider

    W. Elmenreich, W. Haidinger, P. Peti, L. Schneider:
    "New Node Integration for Master-Slave Fieldbus Networks";
    Vortrag: IASTED International Conference on Applied Informatics, Innsbruck, Austria; 18.02.2002 - 21.02.2002; in: "Proceedings of the 20th International Conference on Applied Informatics (AI 2002)", (2002), S. 173 - 176.

    Zusätzliche Informationen

  154. Autor/innen: Wilfried Elmenreich, E182 - 1; Richard Ipp

    W. Elmenreich, R. Ipp:
    "Introduction to TTP/C and TTP/A";
    Vortrag: Workshop on Time-Triggered and Real-Time Communication Systems, Manno, Switzerland (eingeladen); 02.12.2003; in: "Proceedings of the Workshop on Time-Triggered and Real-Time Communication Systems", (2003), 9 S.

    Zusätzliche Informationen

  155. Autor/innen: Wilfried Elmenreich, E182 - 1; Gabor Karsai

    W. Elmenreich, G. Karsai:
    "Transatlantic Collaboration on Model-Integrated Computing for Dependable Embedded Components and Systems";
    Vortrag: Workshop on the Collaboration between FP6/ISTand NSF/ITR Projects, Ljubljana, Slovenia; 20.10.2005; in: "Workshop on the Collaboration between FP6/ISTand NSF/ITR Projects", Information Society Technologies/National Science Foundation, (2005), 5 S.

    Zusätzliche Informationen

  156. Autor/innen: Wilfried Elmenreich, E182 - 1; Gernot Klingler, E182 - 1
    Andere beteiligte Personen: Alexander Gelbukh, CIC-IPN; Ángel Fernando Kuri Morales, ITAM

    W. Elmenreich, G. Klingler:
    "Genetic Evolution of a Neural Network for the Autonomous control of a Four-Wheeled Robot";
    Vortrag: Mexican International Conference on Artificial Intelligence, Aguascalientes, Mexico; 04.11.2007 - 10.11.2007; in: "Sixth Mexican International Conference on Artificial Intelligence", A. Gelbukh, á. Kuri Morales (Hrg.); IEEE Computer Society, (2007), ISBN: 978-0-7695-3124-3; S. 396 - 406.

    Zusätzliche Informationen

  157. Autor/innen: Wilfried Elmenreich, E182 - 1; Stefan Viktor Krywult
    Andere beteiligte Person: Stefan Viktor Krywult

    W. Elmenreich, S. V. Krywult:
    "A Comparison of Fieldbus Protocols: LIN 1.3, LIN 2.0, and TTP/A";
    Vortrag: ETFA, Catania, Italy; 19.09.2005 - 22.09.2005; in: "Proceedings of the 10th IEEE Internationla Conference on Emerging Technologies and Factory Automation", S. V. Krywult (Hrg.); IEEE, I (2005), ISBN: 0-7803-9402-x; S. 747 - 753.

    Zusätzliche Informationen

  158. Autor/innen: Wilfried Elmenreich, E182 - 1; Roman Obermaisser, Universität Siegen

    W. Elmenreich, R. Obermaisser:
    "A Standardized Smart Transducer Interface";
    Vortrag: IEEE International Symposium on Industrial Electronics, L'Aquila, Italy; 08.07.2002 - 11.07.2002; in: "Proceedings of the IEEE International Symposium on Industrial Electronics (ISIE'02)", (2002).

    Zusätzliche Informationen

  159. Autor/innen: Wilfried Elmenreich, E182 - 1; Roman Obermaisser, Universität Siegen; Philipp Peti, E182 - 1

    W. Elmenreich, R. Obermaisser, P. Peti:
    "A Model for Reactive Systems Supporting Varying Degrees of Synchrony";
    Vortrag: IEEE International Conference on Computational Cybernetics, Siofok, Hungary; 29.08.2003 - 31.08.2003; in: "Proceedings of IEEE International Conference on Computational Cybernetics ", (2003), ISBN: 963-7154-18-3; S. 275 - 280.

    Zusätzliche Informationen

  160. Autor/innen: Wilfried Elmenreich, E182 - 1; Christian Paukovits, E182 - 1; Stefan Pitzek, E182 - 1
    Andere beteiligte Person: Wilfried Elmenreich, E182 - 1

    W. Elmenreich, C. Paukovits, S. Pitzek:
    "Automatic Generation of Schedules for Time-Triggered Embedded Transducer Networks";
    Vortrag: ETFA, Catania, Italy; 19.09.2005 - 22.09.2005; in: "Proceedings of the 10th IEEE International Conference on Emerging Technologies and Factory Automation", W. Elmenreich (Hrg.); IEEE, II (2005), ISBN: 0-7803-9402-x; S. 535 - 541.

    Zusätzliche Informationen

  161. Autor/innen: Wilfried Elmenreich, E182 - 1; Philipp Peti, E182 - 1

    W. Elmenreich, P. Peti:
    "Achieving Dependability in Time-Triggered Networks by Sensor Fusion";
    Vortrag: IEEE International Conference on Intelligent Engineering Systems, Opatija, Croatia; 26.05.2002 - 28.05.2002; in: "Proceedings of the 6th IEEE International Conference on Intelligent Engineering Systems (INES)", (2002), S. 167 - 172.

    Zusätzliche Informationen

  162. Autor/innen: Wilfried Elmenreich, E182 - 1; Hubert Piontek, Univ. Ulm; Jörg Kaiser, Univ. Magdeburg

    W. Elmenreich, H. Piontek, J. Kaiser:
    "Interface Design for Real-Time Smart Transducer Networks - Examining COSMIC, LIN, and TTP/A as Case Study";
    Vortrag: International Conference on Real-Time and Network Systems (RTNS), Nancy, France; 29.03.2007 - 30.03.2007; in: "Proceedings of the 15th International Conference on Real-Time and Network Systems", Institut National Polytechnique de Lorraine, Nancy, France (2007), ISBN: 2-905267-53-4; S. 195 - 204.

    Zusätzliche Informationen

  163. Autor/innen: Wilfried Elmenreich, E182 - 1; Stefan Pitzek, E182 - 1

    W. Elmenreich, S. Pitzek:
    "Smart Transducers - Principles, Communications, and Configuration";
    Vortrag: 7th IEEE International Conference on Intelligent Engineering Systems (INES), Assuit, Luxor, Egypt; 04.03.2003 - 06.03.2003; in: "Proceedings of the 7th IEEE International Conference on Intelligent Engineering Systems (INES)", (2003), S. 510 - 515.

    Zusätzliche Informationen

  164. Autor/innen: Wilfried Elmenreich, E182 - 1; Stefan Pitzek, E182 - 1

    W. Elmenreich, S. Pitzek:
    "The Time-Triggered Sensor Fusion Model";
    Vortrag: IEEE International Conference on Intelligent Engineering Systems, Helsinki, Stockholm; 01.09.2001; in: "Proceedings of the 5th IEEE International Conference on Intelligent Engineering Systems (INES)", (2001), S. 297 - 300.

    Zusätzliche Informationen

  165. Autor/innen: Wilfried Elmenreich, E182 - 1; Stefan Pitzek, E182 - 1

    W. Elmenreich, S. Pitzek:
    "Using Sensor Fusion in a Time-Triggered Network";
    Vortrag: Annual Conference of the IEEE Industrial Electronics Society, Denver, Colorado, USA; 29.11.2001 - 02.12.2001; in: "Proceedings of the 27th Annual conference of the IEEE Industrial Electronics Society", (2001), S. 369 - 374.

    Zusätzliche Informationen

  166. Autor/innen: Wilfried Elmenreich, E182 - 1; Stefan Pitzek, E182 - 1; Martin Schlager, E182 - 1

    W. Elmenreich, S. Pitzek, M. Schlager:
    "Modeling Distributed Embedded Applications on an Interface File System";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Vienna, Austria; 12.05.2004 - 14.05.2004; in: "Proceedings of the Seventh IEEE International Symposium on Object-Oriented Real-Time Distributed Computing", IEEE Computer Society Press, (2004), ISBN: 0-7695-2124-x; S. 175 - 182.

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  167. Autor/innen: Wilfried Elmenreich, E182 - 1; Maximilian Rosenblattl; Andreas Wolf

    W. Elmenreich, M. Rosenblattl, A. Wolf:
    "Fixed Point Library According to ISO/IEC Standard DTR 18037 for Atmel AVR Processors";
    Vortrag: 5th Workshop on Intelligent Solutions in Embedded Systems - (WISES'07), Madrid; 21.06.2007 - 22.06.2007; in: "Proceedings of the Fifth International Workshop on Intelligent Solutions in Embedded Systems", IEEE, (2007), ISBN: 978-84-89315-47-1; S. 101 - 113.

    Zusätzliche Informationen

  168. Autor/innen: Wilfried Elmenreich, E182 - 1; Martin Schlager, E182 - 1

    W. Elmenreich, M. Schlager:
    "Simulation-based Development of Embedded Sensor Fusion Applications";
    Vortrag: IEEE International Conference on Computational Cybernetics, Wien; 30.08.2004 - 01.09.2004; in: "Proceedings of the 2nd IEEE International Conference on Computational Cybernetics ", (2004), ISBN: 3-902463-01-5; S. 147 - 153.

    Zusätzliche Informationen

  169. Autor/innen: Wilfried Elmenreich, E182 - 1; Lukas Schneider; Raimund Kirner, E182 - 1

    W. Elmenreich, L. Schneider, R. Kirner:
    "A Robust Certainty Grid Algorithm for Robotic Vision";
    Vortrag: IEEE International Conference on Intelligent Engineering Systems, Opatija, Croatia; 26.05.2002 - 28.05.2002; in: "Proceedings of the 6th IEEE International Conference on Intelligent Engineering Systems (INES)", (2002).

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  170. Autor/innen: Wilfried Elmenreich, E182 - 1; Angela Schörgendorfer
    Andere beteiligte Personen: Kenan Tas, Cankaya Uni., Turkey; Dumitru Baleanu, Cankaya Uni., Turkey; J. A. Tenreiro Machado, ISEP, Porto

    W. Elmenreich, A. Schörgendorfer:
    "Fusion of Continuous-Valued Sensor Measurements using Statistical Analysis";
    Vortrag: International Symposium on Mathematical Methods in Engineering, Ankara, Turkey (eingeladen); 27.04.2006 - 29.04.2006; in: "Proceedings of the International Symposium on Mathematical Methods in Engineering", K. Tas, D. Baleanu, J.A.T. Machado (Hrg.); (2006), ISBN: 975-6734-04-3; 10 S.

    Zusätzliche Informationen

  171. Autor/innen: Wilfried Elmenreich, E182 - 1; Christian Trödhandl, E182 - 1; Bettina Weiss, E182 - 2

    W. Elmenreich, C. Trödhandl, B. Weiss:
    "Embedded Systems Home Experimentation";
    Vortrag: Second IASTED International Conference on Education and Technology, Calgary; 17.09.2006 - 19.09.2006; in: "Proceedings of the Second International Conference on Education and Technology", (2006), S. 11 - 15.

    Zusätzliche Informationen

  172. Autor/innen: Martin Elshuber, E182 - 1; Susanne Kandl, E182 - 1; Peter Puschner, E182 - 1

    M. Elshuber, S. Kandl, P. Puschner:
    "Improving System-Level Verification of SystemC Models with SPIN";
    Vortrag: 1st French Singaporean Workshop on Formal Methods and Applications, Singapore; 15.07.2013 - 16.07.2013; in: "1st French Singaporean Workshop on Formal Methods and Applications", (2013), ISBN: 978-3-939897-56-9; 6 S.

    Zusätzliche Informationen

  173. Autor/innen: Janosch Fauster; Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    J. Fauster, R. Kirner, P. Puschner:
    "Intelligent Editor for Writing Worst-Case-Execution-Time-Oriented Programs";
    Vortrag: International Conference on Embedded Software, Philadelphia, PA, USA; 13.10.2003 - 15.10.2003; in: "Proceedings of the 3rd International Conference on Embedded Software (EMSOFT 2003)", (2003), S. 190 - 205.

    Zusätzliche Informationen

  174. Autor/in: Markus Ferringer, E182 - 2

    M. Ferringer:
    "Conversion and Interfacing Techniques for Asynchronous Circuits";
    Vortrag: 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011), Cottbus, Germany; 13.04.2011 - 15.04.2011; in: "Design and Diagnostics of Electronic Circuits & Systems", (2011), ISBN: 978-1-4244-9755-3; S. 11 - 16.

    Zusätzliche Informationen

  175. Autor/in: Markus Ferringer, E182 - 2

    M. Ferringer:
    "Conversion of Two- to Four-Phase Delay-Insensitive Asynchronous Circuits";
    Vortrag: EUROCON 2011, Lisbon; 27.04.2011 - 29.04.2011; in: "EUROCON - International Conference on Computer as a Tool (EUROCON), 2011 IEEE", (2011), ISBN: 978-1-4244-7486-8; S. 1 - 4.

    Zusätzliche Informationen

  176. Autor/in: Markus Ferringer, E182 - 2

    M. Ferringer:
    "Coupling Asynchronous Signals into Asynchronous Logic";
    Poster: Austrochip, Graz, Austria; 07.09.2009 - 08.09.2009; in: "Austrochip", Institut für Elektronik - TU Graz, (2009), ISBN: 978-3-9501635-1-3; S. 97 - 102.

    Zusätzliche Informationen

  177. Autor/in: Markus Ferringer, E182 - 2

    M. Ferringer:
    "Investigating Self-Timed Circuits for the Time-Triggered Protocol";
    Vortrag: 5th International Workshop on Reconfigurable Communication Centric System-on-Chips, Workshop Proceedings (ReCoSoC), Karlsruhe, Germany; 17.05.2010 - 19.05.2010; in: "Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010", KIT Scientific Publishing - DFG, (2010), ISBN: 9783866445154; S. 101 - 108.

    Zusätzliche Informationen

  178. Autor/in: Markus Ferringer, E182 - 2

    M. Ferringer:
    "Investigating the Impact of Process Variations on an Asynchronous Time-Triggered-Protocol Controller";
    Vortrag: Dependable Systems and Networks Workshops (DSN-W), 2011 IEEE/IFIP 41st International Conference on, Hong-Kong; 27.06.2011 - 30.06.2011; in: "Dependable Systems and Networks Workshops", (2011), ISBN: 978-1-4577-0374-4; S. 47 - 52.

    Zusätzliche Informationen

  179. Autor/in: Markus Ferringer, E182 - 2

    M. Ferringer:
    "Towards self-timed logic in the Time-Triggered Protocol";
    Vortrag: DSN 2010 (International Conference on Dependable Systems and Networks), Chicago, IL, USA; 28.04.2010 - 30.04.2010; in: "DSN 2010 - Full Program", IEEE Computer Society, (2010), ISBN: 9781424477289; S. 136 - 141.

    Zusätzliche Informationen

  180. Autor/innen: Markus Ferringer, E182 - 2; Gottfried Fuchs, E182 - 2; Andreas Steininger, E182 - 2; Gerald Kempf

    M. Ferringer, G. Fuchs, A. Steininger, G. Kempf:
    "VLSI Implementation of a Fault-Tolerant Distributed Clock Generation";
    Vortrag: International Symp. on Defect and Fault Tolerance in VLSI-Systems, Arlington; 04.10.2006 - 06.10.2006; in: "The 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems", (2006), S. 563 - 571.

    Zusätzliche Informationen

  181. Autor/innen: Christof Fetzer; Ulrich Schmid, E182 - 2

    C. Fetzer, U. Schmid:
    "Brief Announcement: On the Possibility of Consensus in Asynchronous Systems with Finite Average Response Times";
    Vortrag: 23th ACM SIGACT-SIGOPS Symposium on Principles of Distributed Computing (PODC), St. John´s , Newfoundland, Canada; 25.07.2004 - 28.07.2004; in: "23th ACM SIGACT-SIGOPS Symposium on PRINCIPLES of DISTRIBUTED commuting (PODC)", (2004), S. 402.

    Zusätzliche Informationen

  182. Autor/innen: Wolfgang Forster; Christof Kutschera; Andreas Steininger, E182 - 2; Karl Michael Göschka, E184 - 1

    W. Forster, C. Kutschera, A. Steininger, K. Göschka:
    "Automated Generation of Explicit Connectors for Component Based Hardware/Software Interaction in Embedded Real-Time Systems";
    Vortrag: 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS 2008), (IPDPS 2008), Miami, Florida, USA; 14.04.2008; in: "Proceedings of the 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS 2008), (IPDPS 2008)", IEEE Computer Society, (2008), ISBN: 978-1-4244-1694-3; S. 1 - 8.

  183. Autor/innen: Werner Friesenbichler, Austrian Aerospace; Thomas Panhofer; Martin Delvai, E182 - 2

    W. Friesenbichler, T. Panhofer, M. Delvai:
    "Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits";
    Vortrag: 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008, Bratislava, Slovakia; 16.04.2008 - 18.04.2008; in: "Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on", IEEE, (2008), ISBN: 978-1-4244-2276-0; S. 267 - 270.

    Zusätzliche Informationen

  184. Autor/innen: Werner Friesenbichler, Austrian Aerospace; Thomas Panhofer; Andreas Steininger, E182 - 2

    W. Friesenbichler, T. Panhofer, A. Steininger:
    "A Deterministic Approach for Hardware Fault Injection in Asynchronous QDI Logic";
    Vortrag: DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria; 14.04.2010 - 16.04.2010; in: "13th IEEE International Symposium On Design And Diagnostics Of Electronic Cicruits And Systems", IEEE, (2010), ISBN: 9781424466108; S. 317 - 322.

    Zusätzliche Informationen

  185. Autor/innen: Werner Friesenbichler, Austrian Aerospace; Thomas Panhofer; Andreas Steininger, E182 - 2

    W. Friesenbichler, T. Panhofer, A. Steininger:
    "Implementation of Self-Healing Asynchronous Circuits at the Example of a Video-Processing Algorithm";
    Vortrag: WSDN 2010 (4th Workshop on Dependable and Secure Nanocomputing, Chicago, IL, USA; 28.06.2010 - 01.07.2010; in: "WSDN - Full Program", IEEE Computer Socitey, (2010), ISBN: 9781424477289; S. 129 - 134.

    Zusätzliche Informationen

  186. Autor/innen: Werner Friesenbichler, Austrian Aerospace; Thomas Panhofer; Andreas Steininger, E182 - 2

    W. Friesenbichler, T. Panhofer, A. Steininger:
    "Reliability Estimation and Experimental Results of a Self-Healing Asynchronous Circuit: A Case Study";
    Vortrag: NASA/ESA 2010 (Conference on Adaptive Hardware and Systems), Anaheim, CA, USA; 15.06.2010 - 18.06.2010; in: "NASA/ESA 2010 Proceedings", IEEE Computer Society, (2010), ISBN: 9781424458882; S. 97 - 104.

    Zusätzliche Informationen

  187. Autor/innen: Werner Friesenbichler, Austrian Aerospace; Andreas Steininger, E182 - 2

    W. Friesenbichler, A. Steininger:
    "Soft Error Tolerant Asynchronous Circuits based on Dual Redundant Four State Logic";
    Vortrag: DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece; 27.08.2009 - 29.08.2009; in: "12th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - Architectures, Methods and Tools - DSD 2009", IEEE Computer Society, (2009), ISBN: 9780769537825; S. 100 - 107.

    Zusätzliche Informationen

  188. Autor/innen: Bernhard Fritz; Savulimedu Veeravall Varadan, E182 - 2; Andreas Steininger, E182 - 2

    B. Fritz, S. Varadan, A. Steininger:
    "Reliable Gateway for Radiation Experiments on a VLSI Chip";
    Poster: Austrochip 2012, Graz, Austria; 10.10.2012; in: "Austrochip 2012", (2012), S. 65 - 70.

    Zusätzliche Informationen

  189. Autor/in: Gottfried Fuchs, E182 - 2

    G. Fuchs:
    "Implications of VLSI Fault Models and Distributed Systems Failure Models --- A Hardware Designer's View";
    Vortrag: Dagstuhl Seminar 08371 : Fault-Tolerant Distributed Algorithms on VLSI Chips, Dagstuhl, Germany; 07.09.2009 - 10.09.2009; in: "Fault-Tolerant Distributed Algorithms on VLSI Chips", Leibniz Zentrum Informatik, 08371 (2009), ISSN: 1862-4405; S. ?.

    Zusätzliche Informationen

  190. Autor/innen: Gottfried Fuchs, E182 - 2; Matthias Függer, E182 - 2; Ulrich Schmid, E182 - 2; Andreas Steininger, E182 - 2

    G. Fuchs, M Függer, U. Schmid, A. Steininger:
    "Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip";
    Vortrag: 11th EUROMICRO Conference on Digital System Design (DSD 2008), Parma, Italien; 03.09.2008 - 05.09.2008; in: "11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008.", IEEE, (2008), ISBN: 978-0-7695-3277-6; S. 242 - 249.

    Zusätzliche Informationen

  191. Autor/innen: Gottfried Fuchs, E182 - 2; Matthias Függer, E182 - 2; Andreas Steininger, E182 - 2

    G. Fuchs, M Függer, A. Steininger:
    "On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme";
    Vortrag: ASYNC 2009 (International Symposium on Asynchronous Circuits and Systems), Chapel Hill, North Carolina; 17.05.2009 - 20.05.2009; in: "ASYNC 2009", IEEE Computer Society, (2009), ISSN: 1522-8681; S. 127 - 136.

    Zusätzliche Informationen

  192. Autor/innen: Gottfried Fuchs, E182 - 2; Matthias Függer, E182 - 2; Andreas Steininger, E182 - 2; Franz Zangerl

    G. Fuchs, M Függer, A. Steininger, F. Zangerl:
    "Analysis of Constraints in a Fault-Tolerant Distributed Clock Generation Scheme";
    Vortrag: 3rd International Workshop on Dependable Embedded Systems, Leeds; 01.10.2006; in: "WDES 2006 3rd Workshop on Dependable Embedded Systems", (2006), S. 22 - 27.

    Zusätzliche Informationen

  193. Autor/innen: Gottfried Fuchs, E182 - 2; Julian Grahsl; Ulrich Schmid, E182 - 2; Andreas Steininger, E182 - 2; Gerald Kempf

    G. Fuchs, J. Grahsl, U. Schmid, A. Steininger, G. Kempf:
    "Threshold Modules -- Die Schlüsselelemente zur Verteilten Generierung eines Fehlertoleranten Taktes";
    Vortrag: Austrochip, Wien; 11.10.2006; in: "Austrochip Mikroelektroniktagung", (2006), S. 149 - 156.

    Zusätzliche Informationen

  194. Autor/innen: Matthias Függer, E182 - 2; Andreas Dielacher, E182 - 2; Ulrich Schmid, E182 - 2

    M Függer, A. Dielacher, U. Schmid:
    "How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining";
    Vortrag: EDCC - 8 (European Dependable Computing Conference), Valencia, Spain; 28.04.2010 - 30.04.2010; in: "Proceedings of the Eight European Dependable Computing Conference", IEEE Computer Society, (2010), ISBN: 9780769540078; S. 230 - 239.

    Zusätzliche Informationen

  195. Autor/innen: Matthias Függer, E182 - 2; Gottfried Fuchs, E182 - 2; Andreas Steininger, E182 - 2

    M Függer, G. Fuchs, A. Steininger:
    "On the Stability and Robustness of Non-Synchronous Circuits with Timing Loops";
    Vortrag: WSDN 2009 (Workshop on Dependable and Secure Nanocomputing, Estoril, Lisbon, Portugal; 29.06.2009 - 30.06.2009; in: "WSDN 2009", Springer, (2009), ISBN: 9781424444212; S. 45 - 50.

    Zusätzliche Informationen

  196. Autor/innen: Matthias Függer, E182 - 2; Thomas Handl, E182 - 2; Andreas Steininger, E182 - 2; Josef Widder, E182 - 2; Christian Tögel

    M Függer, T. Handl, A. Steininger, J. Widder, C. Tögel:
    "An Efficient Test for a Transition Signalling based Up-/Down-Counter";
    Poster: Austrochip, Wien; 11.10.2006; in: "Austrochip Mikroelektroniktagung", (2006), S. 55 - 62.

    Zusätzliche Informationen

  197. Autor/innen: Matthias Függer, E182 - 2; Alexander Kößler, E182 - 2; Thomas Nowak; Ulrich Schmid, E182 - 2; Martin Zeiner, E182 - 2

    M Függer, A. Kößler, T. Nowak, U. Schmid, M. Zeiner:
    "The Effect of Forgetting on the Performance of a Synchronizer";
    Vortrag: ALGOSENSORS 2013 (9th International Symposium on Algorithms and Experiments for Sensor Systems, Wireless Networks and Distributed Robotics), Sophia Antipolis, France; 05.09.2013 - 06.09.2013; in: "Algorithms for Sensor Systems", (2013), S. 185 - 200.

  198. Autor/innen: Matthias Függer, E182 - 2; Alexander Kößler, E182 - 2; Thomas Nowak; Martin Zeiner, E104 - 5

    M Függer, A. Kößler, T. Nowak, M. Zeiner:
    "Brief Announcement: The Degrading Effect of Forgetting on a Synchronizer";
    Vortrag: 14th International Symposium on Stabilization, Safety, and Security of Distributed Systems (SSS 2012), Toronto, Canada; 01.10.2012 - 04.10.2012; in: "Stabilization, Safety, and Security of Distributed Systems", Lecture Notes in Computer Science, 7596 (2012), ISBN: 978-3-642-33535-8; S. 90 - 91.

  199. Autor/innen: Matthias Függer, E182 - 2; Robert Najvirt, E182 - 2; Thomas Nowak; Ulrich Schmid, E182 - 2

    M Függer, R. Najvirt, T. Nowak, U. Schmid:
    "Towards binary circuit models that faithfully capture physical solvability";
    Vortrag: Design, Automation & Test in Europe Conference & Exhibition (DATE'15), Grenoble, France; 09.03.2015 - 13.03.2015; in: "Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE'15)", (2015), ISBN: 978-3-9815370-4-8; S. 1455 - 1460.

  200. Autor/innen: Matthias Függer, E182 - 2; Thomas Nowak; Ulrich Schmid, E182 - 2

    M Függer, T. Nowak, U. Schmid:
    "Unfaithful Glitch Propagation in existing Binary Circuit Models";
    Vortrag: 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2013), Santa Monica, CA; 19.05.2013 - 22.05.2013; in: "Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on", (2013), ISSN: 1522-8681; S. 191 - 199.

  201. Autor/innen: Matthias Függer, E182 - 2; Ulrich Schmid, E182 - 2; Gottfried Fuchs, E182 - 2; Gerald Kempf

    M Függer, U. Schmid, G. Fuchs, G. Kempf:
    "Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip";
    Vortrag: European Dependable Computing Conference, Coimbra; 18.10.2006 - 20.10.2006; in: "EDCC-6", (2006), S. 87 - 96.

    Zusätzliche Informationen

  202. Autor/innen: Matthias Függer, E182 - 2; Josef Widder, E184 - 4

    M Függer, J. Widder:
    "Efficient Checking of Link-Reversal-Based Concurrent Systems";
    Vortrag: International Conference on Concurrency Theory (CONCUR), Newcaslte upon Tyne, UK; 03.09.2012 - 08.09.2012; in: "CONCUR 2012 - Concurrency Theory", Lecture Notes in Computer Science. Springer Verlag., 7454 (2012), ISBN: 978-3-642-32939-5; S. 486 - 499.

    Zusätzliche Informationen

  203. Autor/innen: Raffaele Gallo, E182 - 2; Martin Delvai, E182 - 2; Wilfried Elmenreich, E182 - 1; Andreas Steininger, E182 - 2

    R. Gallo, M. Delvai, W. Elmenreich, A. Steininger:
    "Revision and Verification of an Enhanced UART";
    Vortrag: IEEE International Workshop on Factory Communication Systems, Vienna, Austria; 22.09.2004 - 24.09.2004; in: "Proceedings of the 2004 IEEE International Workshop on Factory Communication Systems", IEEE, (2004), ISBN: 0-7803-8734-1; S. 315 - 318.

    Zusätzliche Informationen

  204. Autor/innen: Clemens Geyer; Benedikt Huber, E182 - 1; Daniel Prokesch, E182 - 1; Peter Puschner, E182 - 1

    C. Geyer, B. Huber, D. Prokesch, P. Puschner:
    "Time-Predictable Code Execution - Instruction-Set Support for the Single-Path Approach";
    Vortrag: 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC 2013), Paderborn, Deutschland; 19.06.2013 - 21.06.2013; in: "Proc. 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC 2013)", (2013).

  205. Autor/innen: Julian Grahsl; Thomas Handl, E182 - 2; Andreas Steininger, E182 - 2

    J. Grahsl, T. Handl, A. Steininger:
    "Exploring the Usefulness of the Gate-level Stuck-at Fault Model for Muller C-Elements";
    Poster: 20. GI/ITG/GMM Workshop Testmethoden und Vuverlässigkeit von Schaltungen und Systemen, Wien; 24.02.2008 - 26.02.2008; in: "20. Workshop Testmethoden und Vuverlässigkeit von Schaltungen und Systemen", (2008), S. 165 - 169.

    Zusätzliche Informationen

  206. Autor/innen: Julian Grahsl; Thomas Handl, E182 - 2; Andreas Steininger, E182 - 2; Gerald Kempf

    J. Grahsl, T. Handl, A. Steininger, G. Kempf:
    "SAFE - A Scalable Environment for Automated Transistor Level Fault Effect Analysis";
    Vortrag: Austrochip, Graz; 11.10.2007; in: "Austrochip - Workshop on Microelectronics", (2007), S. 91 - 98.

    Zusätzliche Informationen

  207. Autor/innen: Günther Gridling, E183 - 1; Bernd Thallner, E182 - 2

    G. Gridling, B. Thallner:
    "Simulation of a Wireless CDMA ad hoc network";
    Vortrag: IASTED Int. Conf. Communictions and Computer Networks, Cambridge, USA; 04.11.2002 - 06.11.2002; in: "Proceedings of the IASTED Internatonal Conference on Communications and Computer Networks", (2002), ISBN: 0-88986-329-6; S. 354 - 359.

  208. Autor/innen: Günther Gridling, E183 - 1; Bettina Weiss, E182 - 2

    G. Gridling, B. Weiss:
    "A µController Lab for Distance Learning";
    Vortrag: 6th International Workshop on Microelectronics Education, Stockholm; 08.06.2006 - 09.06.2006; in: "EWME 2006 - Proceedings", (2006), S. 129 - 132.

    Zusätzliche Informationen

  209. Autor/innen: Günther Gridling, E183 - 1; Bettina Weiss, E182 - 2; Wilfried Elmenreich, E182 - 1; Christian Trödhandl, E182 - 1

    G. Gridling, B. Weiss, W. Elmenreich, C. Trödhandl:
    "Embedded Systems Exams With True/False Questions: A Case Study";
    Vortrag: Second IASTED International Conference on Education and Technology, Calgary; 17.07.2006 - 19.07.2006; in: "Proceedings of the Second International Conference on Education and Technology", (2006), S. 168 - 172.

    Zusätzliche Informationen

  210. Autor/innen: Petr Grillinger, E182 - 1; Astrit Ademaj, E182 - 1; Klaus Steinhammer, E182 - 1; Hermann Kopetz, E182 - 1

    P. Grillinger, A. Ademaj, K. Steinhammer, H. Kopetz:
    "Software Implementation of Time-Triggered Ethernet Controller";
    Vortrag: IEEE International Workshop on Factory Communication Systems, Torino, Italy; 28.06.2006 - 30.06.2006; in: "Workshop on Factory Communication Systems - WFCS 2006, Proceedings", (2006), ISBN: 1-4244-0379-0; S. 145 - 150.

    Zusätzliche Informationen

  211. Autor/innen: Radu Grosu, E182 - 1; Gregory Batt; Flavio H. Fenton, Cornell U.; James Glimm, Stony Brook U; Colas Le Guernic; Scott A. Smolka, Stony Brook U; Ezio Bartocci, E182 - 1

    R. Grosu, G. Batt, F. Fenton, J. Glimm, C. Le Guernic, S. Smolka, E. Bartocci:
    "From Cardiac Cells to Genetic Regulatory Network";
    Vortrag: CAV 2011: the 23rd International Conference on Computer Aided Verification, Snowbird, UT, USA; 14.07.2011 - 20.07.2011; in: "CAV 2011: the 23rd International Conference on Computer Aided Verification", LNCS / Springer, vol. 6806 (2011), ISSN: 0302-9743; S. 396 - 411.

    Zusätzliche Informationen

  212. Autor/innen: Radu Grosu, E182 - 1; Sergiy Bogomolov, Univ. Freiburg; Goran Frehse, Verimag; Marius Greitschus; Corina Pasareanu; Andreas Podelski, Univ. Freiburg; Thomas Strump

    R. Grosu, S. Bogomolov, G. Frehse, M. Greitschus, C. Pasareanu, A. Podelski, T. Strump:
    "Assume-Guarantee Abstraction-Refinement Meets Hybrid Systems";
    Vortrag: Haifa Verification Conference HVC 2014, Haifa, Isral; 18.11.2014 - 20.11.2014; in: "Proc. of HVC'14, the Haifa Verification Conference", (2014).

  213. Autor/innen: Radu Grosu, E182 - 1; Ariful Islam; Abhishek Murthy, Stony Brook U; Antoine Girard; Scott A. Smolka, Stony Brook U

    R. Grosu, A. Islam, A. Murthy, A. Girard, S. Smolka:
    "Compositionality Results for Cardiac Cell Dynamics";
    Vortrag: HSCC'14, the 17th International Conference on Hybrid Systems: Computation and Conrol, Berlin; 15.04.2014 - 17.04.2014; in: "Proc. of HSCC'14, the 17th International Conference on Hybrid Systems: Computation and Control", (2014), ISBN: 978-1-4503-2732-9; S. 243 - 252.

  214. Autor/innen: Radu Grosu, E182 - 1; Doron Peled; C.R. Ramakrishnan; Scott A. Smolka, Stony Brook U; Scott D. Stoller, Stony Brook U; Junxing Yang

    R. Grosu, D. Peled, C. Ramakrishnan, S. Smolka, S. Stoller, J. Yang:
    "Using Statistical Model Checking for Measuring Systems";
    Vortrag: 6th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation (ISoLA 2014), Corfu; 08.10.2014 - 11.10.2014; in: "Proc. of ISoLA'14, the 6th International Symposium on Leveraging Applications of Formal Methods, Verification and Validation", (2014).

  215. Autor/innen: Flavius Gruian; Per Andersson; Krzysztof Kuchcinsky; Martin Schoeberl, E182 - 1

    F. Gruian, P. Andersson, K. Kuchcinsky, M. Schoeberl:
    "Automatic Generation of Application-Specific Systems Based on a Micro-programmed Java Core";
    Vortrag: ACM Symposium on Applied Computing, Santa Fe, New Mexico; 11.03.2005 - 17.03.2005; in: "Proceedings of the 2005 ACM symposium on Applied computing", ACM Press, (2005), ISBN: 1-58113-964-0; S. 879 - 884.

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  216. Autor/innen: Amit Gurung; Deka Arup Kumar; Ezio Bartocci, E182 - 1; Sergiy Bogomolov, Univ. Freiburg; Radu Grosu, E182 - 1; Rajarshi Ray

    A. Gurung, D. Kumar, E. Bartocci, S. Bogomolov, R. Grosu, R. Ray:
    "Parallel Reachability Analysis for Hybrid Systems";
    Vortrag: Proc. of MEMOCODE 2016: the 14th ACM-IEEE International Conference on Formal Methods and Models for System Design, ACM, 2016, Kanpur, India; 18.11.2016 - 20.11.2016; in: "Proc. of MEMOCODE 2016: the 14th ACM-IEEE International Conference on Formal Methods and Models for System Design, ACM, 2016", (2016), S. 12 - 22.

  217. Autor/innen: Jan Gustafsson; Björn Lisper; Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    J. Gustafsson, B. Lisper, R. Kirner, P. Puschner:
    "Input-Dependency Analysis for Hard Real-Time Software";
    Vortrag: IEEE International Workshop on Object-Oriented Real-Time Dependable Systems, Capri, Italy; 01.10.2003 - 03.10.2003; in: "Proceedings of the 9th IEEE International Workshop on Object-oriented Real-time Dependable Systems (WORDS'03F)", (2003), S. 1 - 8.

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  218. Autor/innen: Iman Haghighi; Austin Jones; Jones Zhaodan Kong; Ezio Bartocci, E182 - 1; Radu Grosu, E182 - 1; Calin Belta, Boston University

    I. Haghighi, A. Jones, J. Kong, E. Bartocci, R. Grosu, C. Belta:
    "SpaTeL: A Novel Spatial-Temporal Logic and Its Applications to Networked Systems";
    Vortrag: 18th International Conference on Hybrid Systems: Computation and Control (HSCC), Seattle, USA; 13.04.2015 - 15.04.2015; in: "Proc. of HSCC 2015: the 18th International Conference on Hybrid Systems: Computation and Control", ACM, (2015), ISBN: 978-1-4503-3433-4; S. 189 - 198.

  219. Autor/innen: Thomas Handl, E182 - 2; Andreas Steininger, E182 - 2

    T. Handl, A. Steininger:
    "Implementation of an FPGA-Based Hardware Fault Injector";
    Poster: Junior Scientist Conference, Wien; 19.04.2006 - 21.04.2006; in: "Junior Scientist Conference 2006", (2006), S. 23 - 24.

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  220. Autor/innen: Thomas Handl, E182 - 2; Andreas Steininger, E182 - 2; Gerald Kempf

    T. Handl, A. Steininger, G. Kempf:
    "Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit";
    Vortrag: International Design and Test Workshop (IDT), Kairo; 16.12.2007 - 18.12.2007; in: "Proceedings IDT'07 - The Second International Design and Test Workshop", (2007), S. 115 - 119.

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  221. Autor/innen: Thomas Handl, E182 - 2; Andreas Steininger, E182 - 2; Gerald Kempf

    T. Handl, A. Steininger, G. Kempf:
    "An Efficient Test Strategy for a Fault-Tolerant Clock Generator for Systems-on-Chip";
    Vortrag: 19. ITG/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Errlangen; 11.03.2007 - 13.03.2007; in: "19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (2007), S. 66 - 70.

    Zusätzliche Informationen

  222. Autor/innen: Sten Hanke; Christopher Mayer; Oliver Höftberger, E182 - 1; Henriette Boos; Reiner Wichert; Peter Wolf

    S. Hanke, C. Mayer, O. Höftberger, H. Boos, R. Wichert, P. Wolf et al.:
    "universAAL - an open and consolidated AAL platform";
    Vortrag: 4. Deutsche AAL-Kongress, Berlin, Deutschland; 25.01.2011 - 26.01.2011; in: "Demographischer Wandel - Assistenzsysteme aus der Forschung in den Markt (AAL 2011)", (2011), ISBN: 978-3-8007-3323-1.

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  223. Autor/innen: Alexander Hanzlik, E182 - 1; Astrit Ademaj, E182 - 1

    A. Hanzlik, A. Ademaj:
    "A Composable Algorithm for Clock Synchronization in Multi-Cluster Real-Time Systems";
    Vortrag: 4th Workshop on Intelligent Solutions in Embedded Systems - (WISES06), Vienna, Austria; 30.06.2006; in: "4th Workshop on Intelligent Solutions in Embedded Systems - (WISES06), Proceedings of the", (2006).

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  224. Autor/innen: Trevor Harmon, UCI; Martin Schoeberl, E182 - 1; Raimund Kirner, E182 - 1; Raymond Klefstad, UCI

    T. Harmon, M. Schoeberl, R. Kirner, R. Klefstad:
    "A Modular Worst-case Execution Time Analysis Tool for Java Processors";
    Vortrag: 14th IEEE Real-Time and Embedded Technology and Applications Symposium, St. Louis, Missouri, USA; 22.04.2008 - 24.04.2008; in: "14th IEEE Real-Time and Embedded Technology and Applications Symposium", IEEE Computer Society, (2008), ISBN: 978-0-7695-3146-5; Paper-Nr. 47, 11 S.

    Zusätzliche Informationen

  225. Autor/innen: Trevor Harmon, UCI; Martin Schoeberl, E182 - 1; Raimund Kirner, E182 - 1; Raymond Klefstad, UCI

    T. Harmon, M. Schoeberl, R. Kirner, R. Klefstad:
    "Toward Libraries for Real-time Java";
    Vortrag: The 11th IEEE Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, Orlando, Florida, USA; 05.05.2008 - 07.05.2008; in: "The 11th IEEE Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing", IEEE Computer Society, (2008), ISBN: 978-0-7695-3132-8; S. 458 - 462.

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  226. Autor/innen: Karl Hendling, E389; Thomas Losert, E182 - 1; Wolfgang Huber, E182 - 2; Martin Jandl, E384

    K. Hendling, T. Losert, W. Huber, M. Jandl:
    "Interference Minimizing Bandwidth Guaranteed On-Line Routing Algorithm for Traffic Engineering";
    Vortrag: IEEE International Conference on Networks (2004, 12th ICON), Singapur; 16.11.2004 - 19.11.2004; in: "Proceedings of the IEEE International Conference on Networks (2004, 12th ICON) ", IEEE, Volume 2 (2004), ISBN: 0-7803-8783-x; S. 497 - 503.

    Zusätzliche Informationen

  227. Autor/innen: Stefan Hepp, E185 - 1; Benedikt Huber, E182 - 1; Jens Knoop, E185 - 1; Daniel Prokesch, E182 - 1; Peter Puschner, E182 - 1

    S Hepp, B. Huber, J. Knoop, D. Prokesch, P. Puschner:
    "The platin Tool Kit - The T-CREST Approach for Compiler and WCET Integration";
    Vortrag: 18. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS) 2015, Pörtschach am Wörthersee; 04.10.2015 - 07.10.2015; in: "18. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS) 2015", (2015).

    Zusätzliche Informationen

  228. Autor/innen: Stefan Hepp; Georg Klima; Albrecht Kadlec, E182 - 1; Lukas Krammer; Werner Luckner; Daniel Prokesch, E182 - 1; Stefan Resch, Thales; Armin Wasicek, E182 - 1; Jakob Wilhelm; Peter Tummeltshammer, E182 - 2; Martin Delvai, E182 - 2

    S. Hepp, G. Klima, A. Kadlec, L. Krammer, W. Luckner, D. Prokesch, S. Resch, A. Wasicek, J. Wilhelm, P Tummeltshammer, M. Delvai:
    "Exploring Hardware Software Partitioning on the Example of a Fingerprint Verification System";
    Vortrag: 16th Austrian Workshop on Microelectronics (Austrochip), Linz; 08.10.2008; in: "Proc. of the 16th Austrian Workshop on Microelectronics 2008", (2008), S. 7 - 12.

  229. Autor/innen: Jean-Francois Hermant; Josef Widder, E182 - 2

    J.-F. Hermant, J. Widder:
    "Implementing Reliable Distributed Real Time Systems with the Theta Model";
    Vortrag: International Conference on Principles of Distributed Systems, Pisa; 12.12.2005 - 14.12.2005; in: "9th International Conference on Principles of Distributed Systems", (2005), S. 259 - 271.

  230. Autor/innen: Wolfgang Herzner, ARC Seibersdorf; Bernhard Huber, E182 - 1; András Balogh, Budapest University; György Csertan

    W. Herzner, B. Huber, A. Balogh, G. Csertan:
    "The DECOS Tool-Chain: Model-Based Development of Distributed Embedded Safety-Critical Real-time Systems";
    Vortrag: SAFECOMP, Gdansk, Poland; 26.09.2006 - 29.09.2006; in: "DECOS/ERCIM Workshop on Dependable Embedded Systems at SAFECOMP 2006, Proceedings", (2006).

    Zusätzliche Informationen

  231. Autor/innen: Wolfgang Herzner, ARC Seibersdorf; Martin Schlager, E182 - 1; Thierry Le Sergent, Esterel Technologies; Bernhard Huber, E182 - 1; Shariful Islam, TU Darmstadt; Neeraj Suri; András Balogh, Budapest University

    W. Herzner, M. Schlager, T. Le Sergent, B. Huber, S. Islam, N. Suri, A. Balogh:
    "From Model-Based Design to Deployment of Integrated, Embedded, Real-Time Systems: The DECOS Tool-Chain";
    Poster: International DECOS Workshop, Vienna, Austria; 11.10.2006 - 13.10.2006; in: "Tagungsband, zur Informationstagung Mikroelektronik", (2006), S. 204 - 213.

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  232. Autor/innen: Oliver Höftberger, E182 - 1; Roman Obermaisser, Universität Siegen

    O. Höftberger, R. Obermaisser:
    "Ontology-based Runtime Reconfiguration of Distributed Embedded Real-Time Systems";
    Vortrag: 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC 2013), Paderborn, Deutschland; 19.06.2013 - 21.06.2013; in: "Proc. 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC 2013)", (2013).

    Zusätzliche Informationen

  233. Autor/innen: Oliver Höftberger, E182 - 1; Roman Obermaisser, Universität Siegen

    O. Höftberger, R. Obermaisser:
    "Runtime Evaluation of Ontology-based Reconfiguration of Distributed Embedded Real-Time Systems";
    Vortrag: 12th IEEE International Conference on Industrial Informatics, Porto Alegre, Brazil; 27.07.2014 - 30.07.2014; in: "Proc. of the 12th IEEE International Conference on Industrial Informatics", (2014), ISBN: 978-1-4799-4906-9; S. 544 - 550.

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  234. Autor/innen: Roland Höller, E384; Martin Horauer, E384; Günther Gridling, E183 - 1; Nikolaus Kerö, E384; Ulrich Schmid, E182 - 2; Klaus Schossmaier, E183 - 1

    R. Höller, M. Horauer, G. Gridling, N. Kerö, U. Schmid, K. Schossmaier:
    "SynUTC - high precision time synchronization over Ethernet networks";
    Vortrag: 8th Workshop on Electronics for LHC Experiments, Colmar; France; 09.09.2002 - 13.09.2002; in: "Proceedings 8th Workshop on Electronics for LHC Experimets (LECC'02)", (2002), ISBN: 92-9083-202-9; S. 428 - 432.

  235. Autor/innen: Michael Hofbauer, E354; Kurt Schweiger, E354; Horst Zimmermann, E354; Ulrich Giesen; Frank Langner; Ulrich Schmid, E182 - 2; Andreas Steininger, E182 - 2

    M. Hofbauer, K. Schweiger, H. Zimmermann, U. Giesen, F. Langner, U. Schmid, A. Steininger:
    "Supply Voltage Dependent On-chip Single Event Transient Pulse Shape Measurements in 90 nm Bulk CMOS under Alpha Irradiation";
    Poster: 21st European Conference on Radiation and its Effects on Components and Systems (RADECS'12), Biarritz, FRANCE; 24.09.2012 - 28.09.2012; in: "Proceedings 21st European Conference on Radiation and its Effects on Components and Systems (RADECS'12)", (2012).

    Zusätzliche Informationen

  236. Autor/innen: Niklas Holsti; Jan Gustafsson; Guillem Bernat; Clément Ballabriga; Armelle Bonenfant; Roman Bourgade; Hugues Cassé; Daniel Cordes; Albrecht Kadlec, E182 - 1; Raimund Kirner, E182 - 1; Jens Knoop, E185 - 1; Paul Lokuciejewski; Nicholas Merriam; Marianne de Michiel; Adrian Prantl, E185 - 1; Bernhard Rieder, E182 - 1; Christine Rochange; Pascal Sainrat; Markus Schordan, E185 - 1

    N. Holsti, J. Gustafsson, G. Bernat, C. Ballabriga, A. Bonenfant, R. Bourgade, H. Cassé, D. Cordes, A. Kadlec, R. Kirner, J. Knoop, P. Lokuciejewski, N. Merriam, M. de Michiel, A. Prantl, B. Rieder, C. Rochange, P. Sainrat, M. Schordan:
    "WCET Tool Challenge 2008: Report";
    Vortrag: WCET 2008, Prague, Czech Republic; 01.07.2008; in: "Worst-Case Execution Time Analysis; Proceedings of the 8th International Workshop (WCET 2008)", Österreichische Computer Gesellschaft, (2008), ISBN: 978-3-85403-237-3; S. 149 - 171.

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  237. Autor/innen: Martin Horauer; Eric Armengaud, E182 - 2; Andreas Steininger, E182 - 2

    M. Horauer, E. Armengaud, A. Steininger:
    "Concepts and Tools for the Test of the Communication Sub-System of Time-Triggered Distributed Embedded Systems";
    Vortrag: International Conference on Design Engineering Technical Conferences & Computers and Information in Engineering (ASME), Las Vegas; 04.09.2007 - 07.09.2007; in: "ASME 2007 International Conference on Design Engineering Technical Conferences & Computers and Information in Engineering", (2007).

    Zusätzliche Informationen

  238. Autor/innen: Martin Horauer; Florian Rothensteiner; Martin Zauner; Eric Armengaud, E182 - 2; Andreas Steininger, E182 - 2; Hannes Friedl; Roman Pallierer, E182 - 1

    M. Horauer, F Rothensteiner, M Zauner, E. Armengaud, A. Steininger, H. Friedl, R. Pallierer:
    "An FPGA based SoC Design for Testing Embedded Automotive Communication Systems employing the FlexRay Protocol";
    Poster: Austrochip, Wien; 2004; in: "Austrochip 2004", TU-Wien, (2004), S. 119 - 123.

    Zusätzliche Informationen

  239. Autor/innen: Martin Horauer; Ulrich Schmid, E182 - 2; Klaus Schossmaier, E183 - 1; Roland Höller, E384; Nikolaus Kerö, E366

    M. Horauer, U. Schmid, K. Schossmaier, R. Höller, N. Kerö:
    "PSynUTC --- evaluation of a high precision time synchronization prototype system for Ethernet LANs.";
    Vortrag: IEEE Precise Time and Time Interval Systems and Application Meeting, Reston, Virginia, USA; 03.12.2002 - 05.12.2002; in: "Proceedings of the 34th IEEE Precise Time and Time Interval Systems and Application Meeting (PTTI'02)", (2003), S. 263 - 278.

  240. Autor/innen: Bernhard Huber, E182 - 1; Christian El Salloum, E182 - 1; Roman Obermaisser, Universität Siegen

    B. Huber, C. El Salloum, R. Obermaisser:
    "A Resource Management Framework for Mixed-Criticality Embedded Systems";
    Vortrag: 34th Annual Conference of the IEEE Industrial Electronics Society (IECON'08), Orlando, FL, U.S.A.; 10.11.2008 - 13.11.2008; in: "34th Annual Conference of the IEEE Industrial Electronics Society (IECON'08)", IEEE Computer Society, (2008), ISBN: 978-1-4244-1766-7; S. 2425 - 2431.

    Zusätzliche Informationen

  241. Autor/innen: Bernhard Huber; Wilfried Elmenreich, E182 - 1

    B. Huber, W. Elmenreich:
    "Wireless Time-Triggered Real-Time Communication";
    Vortrag: Workshop on Intelligent Solutions in Embedded Systems, Graz, Österreich; 25.06.2004; in: "Proceedings of the 2nd Workshop on Intelligent Solutions in Embedded Systems", (2004), ISBN: 3-902463-00-7; S. 169 - 182.

    Zusätzliche Informationen

  242. Autor/innen: Benedikt Huber, E182 - 1; Stefan Hepp, E185 - 1; Martin Schöberl, DTU

    B. Huber, S Hepp, M. Schöberl:
    "Scope-based Method Cache Analysis";
    Vortrag: 14th International Workshop on Worst-Case Execution Time Analysis (WCET 2014), Madrid; 08.07.2014; in: "14th International Workshop on Worst-Case Execution Time Analysis", OpenAccess Series in Informatics (OASIcs), (2014), ISBN: 978-3-939897-69-9; S. 73 - 82.

    Zusätzliche Informationen

  243. Autor/innen: Bernhard Huber, E182 - 1; Roman Obermaisser, Universität Siegen

    B. Huber, R. Obermaisser:
    "A Comparison of NoTA and GENESYS";
    Vortrag: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th InternationalWorkshop, SAMOS 2009, Proceedings, Samos, Greece; 20.07.2009 - 23.07.2009; in: "Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th InternationalWorkshop, SAMOS 2009, Proceedings", LNCS / Springer, 5657 (2009), ISBN: 3-642-03137-4; S. 181 - 192.

    Zusätzliche Informationen

  244. Autor/innen: Bernhard Huber, E182 - 1; Roman Obermaisser, Universität Siegen

    B. Huber, R. Obermaisser:
    "Model-Based Development of Integrated Computer Systems: Modeling the Execution Platform";
    Vortrag: 5th Workshop on Intelligent Solutions in Embedded Systems - (WISES'07), Madrid, Spanien; 21.06.2007 - 22.06.2007; in: "Proceedings of the Fifth International Workshop on intelligent Solutions in Embedded Systems", IEEE, (2007), ISBN: 978-84-89315-47-1; S. 151 - 164.

    Zusätzliche Informationen

  245. Autor/innen: Bernhard Huber, E182 - 1; Roman Obermaisser, Universität Siegen; Philipp Peti, E182 - 1

    B. Huber, R. Obermaisser, P. Peti:
    "MDA-Based Development in the DECOS Integrated Architecture - Modeling the Hardware Platform";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Gyeongju, Korea; 24.06.2006 - 26.06.2006; in: "Proceedings of the 9th IEEE International Symposium on Object and component-oriented Real-time distributed Computing (ISORC'06)", IEEE, (2006), ISBN: 0-7695-2561-x.

    Zusätzliche Informationen

  246. Autor/innen: Bernhard Huber; Philipp Peti, E182 - 1; Roman Obermaisser, Universität Siegen; Christian El Salloum, E182 - 1

    B. Huber, P. Peti, R. Obermaisser, C. El Salloum:
    "Using RTAI/LXRT for Partitioning in a Prototype Implementation of the DECOS Architecture";
    Vortrag: 3rd Workshop on Intelligent Solutions in Embedded Systems (WISES'05), Hamburg, Germany; 20.05.2005; in: "Proceedings of the 3rd Workshop on Intelligent Solutions in Embedded Systems (WISES'05),", (2005), ISBN: 3-902463-03-1; S. 3 - 16.

    Zusätzliche Informationen

  247. Autor/innen: Benedikt Huber, E182 - 1; Daniel Prokesch, E182 - 1; Peter Puschner, E182 - 1

    B. Huber, D. Prokesch, P. Puschner:
    "A Formal Framework for Precise Parametric WCET Formulas";
    Vortrag: 12th International Workshop on Worst-Case Execution Time Analysis (WCET 2012), Pisa; 10.07.2012; in: "12th International Workshop on Worst-Case Execution Time Analysis, WCET 2012", Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Oasics / 23 (2012), ISBN: 978-3-939897-41-5; S. 91 - 102.

    Zusätzliche Informationen

  248. Autor/innen: Benedikt Huber, E182 - 1; Daniel Prokesch, E182 - 1; Peter Puschner, E182 - 1

    B. Huber, D. Prokesch, P. Puschner:
    "Combined WCET analysis of bitcode and machine code using control-flow relation graphs";
    Vortrag: Conference on Languages, Compilers and Tools for Embedded Systems (LCTES 2013), Seattle, WA, USA; 20.06.2013 - 21.06.2013; in: "Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems", The Association for Computing Machinery, (2013), ISBN: 978-1-4503-2085-6; S. 163 - 172.

    Zusätzliche Informationen

  249. Autor/innen: Benedikt Huber, E182 - 1; Wolfgang Puffitsch, E182 - 1; Peter Puschner, E182 - 1

    B. Huber, W. Puffitsch, P. Puschner:
    "Towards an open timing analysis platform";
    Vortrag: 11th International Workshop on Worst-Case Execution Time Analysis, Porto; 05.07.2011; in: "Proceedings of the 11th International Workshop on Worst-Case Execution Time (WCET) Analysis", (2011), S. 6 - 15.

    Zusätzliche Informationen

  250. Autor/innen: Benedikt Huber, E182 - 1; Wolfgang Puffitsch, E182 - 1; Martin Schoeberl

    B. Huber, W. Puffitsch, M. Schoeberl:
    "WCET driven design space exploration of an object cache";
    Vortrag: Workshop on Java Technologies for Real-time and Embedded Systems (JTRES), Prague, Czech Republic; 19.08.2010 - 21.08.2010; in: "WCET driven design space exploration of an object cache", ACM, (2010), ISBN: 978-1-4503-0122-0; S. 26 - 35.

    Zusätzliche Informationen

  251. Autor/innen: Benedikt Huber, E182 - 1; Peter Puschner, E182 - 1

    B. Huber, P. Puschner:
    "A Code Policy Guaranteeing Fully Automated Path Analysis";
    Vortrag: 10th International Workshop on Worst-Case Execution-Time Analysis, Brussels, Belgium; 07.07.2010 - 09.07.2010; in: "A Code Policy Guaranteeing Fully Automated Path Analysis", Austrian Computer Society, (2010), ISBN: 978-3-85403-268-7; S. 80 - 90.

    Zusätzliche Informationen

  252. Autor/innen: Benedikt Huber, E182 - 1; Martin Schoeberl, E182 - 1

    B. Huber, M. Schoeberl:
    "Comparison of Implicit Path Enumeration and Model Checking based WCET Analysis";
    Vortrag: 9th International Workshop on Worst-Case Execution Time (WECT) Analysis, Dublin, Ireland; 30.06.2009; in: "Worst-Case Execution Time (WCET) Analsysis", Austrian Computer Society, 252 (2009), ISBN: 978-3-85403-252-6; S. 27 - 38.

    Zusätzliche Informationen

  253. Autor/innen: Florian Huemer, E182 - 2; Jakob Lechner, E182 - 2; Andreas Steininger, E182 - 2

    F. Huemer, J. Lechner, A. Steininger:
    "A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes";
    Poster: 2016 IEEE International Conference on Computer Design, Phoenix, Arizona, USA; 03.10.2016 - 05.10.2016; in: "Proceedings 2016 IEEE International Conference on Computer Design", (2016), ISBN: 978-1-5090-5142-7; S. 392 - 395.

    Zusätzliche Informationen

  254. Autor/innen: Florian Huemer, E182 - 2; Markus Schütz, E182 - 2; Andreas Steininger, E182 - 2

    F. Huemer, M. Schütz, A. Steininger:
    "Revisiting Sorting Network based Completion Detection for 4 Phase Delay Insensitive Codes";
    Vortrag: Austrochip Workshop on Microelectronics, Wien; 28.09.2015; in: "Austrochip Workshop on Microelectronics", (2015), 6 S.

    Zusätzliche Informationen

  255. Autor/in: Martin Hutle, E182 - 2

    M. Hutle:
    "An efficient failure detector for sparsely connected networks";
    Vortrag: 22nd IASTED International Multi-Conference on Applied Informatics, Innsbruck, Austria; 17.02.2004 - 19.02.2004; in: "Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks ", Acta Press, (2004), ISSN: 1027-2666; S. 369 - 374.

    Zusätzliche Informationen

  256. Autor/in: Martin Hutle, E182 - 2

    M. Hutle:
    "On omega in sparse networks (Fast Abstract)";
    Vortrag: 20th IEEE International Conference on Software Maintenance (ICSM'04), Papeete,Tahiti,French Polynesia; 03.03.2004 - 05.03.2004; in: "Proceedings of the 10th IEEE International Symposium Pacific Rim Dependable Computing ", LAAS-CNRS, (2004), S. 37 - 38.

    Zusätzliche Informationen

  257. Autor/innen: Martin Hutle, E182 - 2; Dahlia Malkhi; Ulrich Schmid, E182 - 2; Lidong Zhou

    M. Hutle, D. Malkhi, U. Schmid, L. Zhou:
    "Brief Announcement: Chasing the Weakest System Model for Implementing Omega and Consensus";
    Vortrag: 8th International Symposium on Stabilization, Safety, and Security of Distributed Systems, Dallas; 17.11.2006 - 19.11.2006; in: "Stabilization, Safety, and Security of Distributed Systems", (2006).

    Zusätzliche Informationen

  258. Autor/innen: Martin Hutle, E182 - 2; Josef Widder, E182 - 2

    M. Hutle, J. Widder:
    "Brief Announcement: On the Possibility and the Impossibility of Message-Driven Self-Stabilizing Failure Detection";
    Vortrag: ACM Symposium on Principles of Distributed Computing, Las Vegas, Nevada; 17.07.2005 - 20.07.2005; in: "Proceedings of the 24th ACM Symposium on Principles of Distributed Computing", (2005), S. 208.

  259. Autor/innen: Martin Hutle, E182 - 2; Josef Widder, E182 - 2

    M. Hutle, J. Widder:
    "On the Possibility and the Impossibility of Message-Driven Self-Stabilizing Failure Detection";
    Vortrag: Seventh International Symposium on Self Stabilizing Systems (SSS 2005), Barcelona, Spanien; 26.10.2005 - 27.10.2005; in: "Self Stabilizing Systems", (2005), S. 153 - 170.

    Zusätzliche Informationen

  260. Autor/innen: Martin Hutle, E182 - 2; Josef Widder, E182 - 2

    M. Hutle, J. Widder:
    "Self-Stabilizing Failure Detector Algorithms";
    Vortrag: IASTED International Conference on Parallel and Distributed Computing Systems, Innsbruck, Austria; 15.02.2005 - 17.02.2005; in: "IASTED International Conference on Parallel and Distributed Computing and Networks", (2005), ISBN: 0-88986-468-3; S. 485 - 490.

    Zusätzliche Informationen

  261. Autor/innen: Haris Isakovic, E182 - 1; Radu Grosu, E182 - 1

    H. Isakovic, R. Grosu:
    "A heterogeneous time-triggered architecture on a hybrid system-on-a-chip platform";
    Vortrag: 2016 IEEE 25th International Symposium on Industrial Electronics (ISIE), Santa Clara, CA, USA; 08.06.2016 - 10.06.2016; in: "IEEE 25th International Symposium on Industrial Electronics (ISIE)", IEEE, (2016), ISSN: 2163-5145; S. 244 - 253.

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  262. Autor/innen: Haris Isakovic, E182 - 1; Armin Wasicek, E182 - 1

    H. Isakovic, A. Wasicek:
    "Secure Channels in an Integrated MPSoC Architecture";
    Vortrag: 39th Annual Conference of the IEEE Industrial Electronics Society, Wien; 10.11.2013 - 13.11.2013; in: "Industrial Electronics Society, IECON 2013 - 39th Annual Conference of the IEEE", (2013), ISSN: 1553-572x; S. 4488 - 4493.

    Zusätzliche Informationen

  263. Autor/innen: Ariful Islam; Greg Byrne; Soonho Kong; Edmund Clarke; Rance Cleaveland; Flavio H. Fenton, Cornell U.; Radu Grosu, E182 - 1; Paul Jones; Scott A. Smolka, Stony Brook U

    A. Islam, G. Byrne, S. Kong, E. Clarke, R. Cleaveland, F. Fenton, R. Grosu, P. Jones, S. Smolka:
    "Bifurcation Analysis of Cardiac Alternans using Delta-Decidability";
    Vortrag: CMSB 2016: 14th International Conference on Computational Methods in Systems Biology, Cambridge, UK; 21.09.2016 - 23.09.2016; in: "Proceedings of CMSB'16, the 14th International Conference on Computational Methods in Systems Biology", LNCS, Springer, Lecture Notes in Computer Science, Vol. 9859, Cambridge, UK (2016), ISBN: 978-3-319-45176-3; S. 132 - 146.

    Zusätzliche Informationen

  264. Autor/innen: Ariful Islam; Qinsi Wang; Ramin M. Hasani, E182 - 1; Ondrej Balún; Edmund Clarke; Radu Grosu, E182 - 1; Scott A. Smolka, Stony Brook U

    A. Islam, Q. Wang, R. M. Hasani, O. Balún, E. Clarke, R. Grosu, S. Smolka:
    "Probabilistic Reachability Analysis of the Tap Withdrawal Circuit in Caenorhabditis elegans";
    Vortrag: 18th IEEE International High-Level Design Validation and Test Workshop (HLDVT) 2016, Santa Cruz, California, U.S.A.; 07.10.2016 - 08.10.2016; in: "18th IEEE International High-Level Design Validation and Test Workshop", IEEE, (2016), ISSN: 2471-7827; S. 170 - 177.

    Zusätzliche Informationen

  265. Autor/innen: Stefan Jaksic; Ezio Bartocci, E182 - 1; Radu Grosu, E182 - 1; Reinhard Kloibhofer; Thang Nguyen; Dejan Nickovic, AIT

    S. Jaksic, E. Bartocci, R. Grosu, R. Kloibhofer, T. Nguyen, D. Nickovic:
    "From Signal Temporal Logic to FPGA Monitors";
    Vortrag: 13th ACM-IEEE International Conference on Formal Methods and Models for System Design, Austin, TX, USA; 21.09.2015 - 23.09.2015; in: "Proc. of MEMOCODE 2015: the 13th ACM-IEEE International Conference on Formal Methods and Models for System Design", IEEE, (2015), S. 218 - 227.

    Zusätzliche Informationen

  266. Autor/innen: Stefan Jaksic; Ezio Bartocci, E182 - 1; Radu Grosu, E182 - 1; Dejan Nickovic, AIT

    S. Jaksic, E. Bartocci, R. Grosu, D. Nickovic:
    "Quantitative Monitoring of STL with Edit Distance";
    Vortrag: 7th International Conference on Runtime Verification, Madrid; 23.12.2016 - 30.12.2016; in: "Runtime Verification - 16th International Conference, RV 2016, Madrid, Spain, September 23-30, 2016, Proceedings", Springer International Publishing, 10012 (2016), ISSN: 0302-9743; S. 201 - 218.

    Zusätzliche Informationen

  267. Autor/innen: Martin Jankela; Wolfgang Puffitsch, E182 - 1; Wolfgang Huber, E182 - 2

    M. Jankela, W. Puffitsch, W. Huber:
    "Towards a Rapid Prototyping Framework for Architecture Exploration in Embedded Systems";
    Vortrag: Workshop on Intelligent Solutions in Embedded Systems, Graz, Austria; 25.06.2004; in: "Proceedings of the Second Workshop on Intelligent Solutions im Embedded Systems", (2004), ISBN: 3902463007; S. 117 - 127.

  268. Autor/innen: Marcus Jeitler, E182 - 2; Martin Delvai, E182 - 2; Stefan Reichör

    M. Jeitler, M. Delvai, S. Reichör:
    "Fuse - A Hardware Accelerated Hdl Fault Injection Tool";
    Vortrag: SPL 2009 (Southern Conference on Programmable Logic), Sao Carlos, Brazil; 01.04.2009 - 03.04.2009; in: "2009", IEEE, (2009), ISBN: 9781424438464; S. 89 - 94.

    Zusätzliche Informationen

  269. Autor/innen: Marcus Jeitler, E182 - 2; Jakob Lechner, E182 - 2

    M. Jeitler, J. Lechner:
    "Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection";
    Vortrag: MEMICS 2009 (Mathematical and Engineering Methods in Computer Science), Znojmo; 13.11.2009 - 15.11.2009; in: "MEMICS 2009 proceedings", Universität Brno, (2009), ISBN: 9788087342046; S. 110 - 117.

    Zusätzliche Informationen

  270. Autor/innen: Marcus Jeitler, E182 - 2; Jakob Lechner, E182 - 2

    M. Jeitler, J. Lechner:
    "Low Latency Recovery from Transient Faults for Pipelined Processor Architectures";
    Vortrag: DSD 2010 (Euromicro Conference on Digital System Design), Lille, France; 01.09.2010 - 03.09.2010; in: "Proceedings DSD 2010 (Euromicro Conference on Digital System Design)", IEEE Computer Society, (2010), ISBN: 9780769541716; S. 219 - 225.

    Zusätzliche Informationen

  271. Autor/innen: Marcus Jeitler, E182 - 2; Jakob Lechner, E182 - 2

    M. Jeitler, J. Lechner:
    "Speeding up Fault Injection for Asynchronous Logic by FPGA-based Emulation";
    Poster: ReConFig 2009 (International Conference on ReConFigurable Computing and FPGAs), Cancun, Quintana Roo, Mexico; 09.12.2009 - 11.12.2009; in: "ReConFig'09", CPS, (2009), ISBN: 9780769539171; S. 65 - 70.

    Zusätzliche Informationen

  272. Autor/innen: Marcus Jeitler, E182 - 2; Jakob Lechner, E182 - 2; Andreas Steininger, E182 - 2

    M. Jeitler, J. Lechner, A. Steininger:
    "Enhancing Pipelined Processor Architectures with Fast Autonomous Recovery of Transient Faults";
    Poster: DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria; 14.04.2010 - 16.04.2010; in: "13th IEEE International Symposium On Design And Diagnostics Of Electronic Cicruits And Systems", IEEE Computer Society, (2010), ISBN: 9781424466108; S. 233 - 236.

    Zusätzliche Informationen

  273. Autor/innen: Annu John, E184 - 4; Igor Konnov, E184 - 4; Ulrich Schmid, E182 - 2; Helmut Veith, E184 - 4; Josef Widder, E184 - 4

    A. John, I. Konnov, U. Schmid, V. Veith, J. Widder:
    "Brief announcement: parameterized model checking of fault-tolerant distributed algorithms by abstraction";
    Vortrag: ACM SIGACT-SIGOPS Symposium on Principles of Distributed Computing (PODC), Montreal, Kanada; 22.07.2013 - 24.07.2013; in: "PODC", ACM, (2013), ISBN: 978-1-4503-2065-8; S. 119 - 121.

  274. Autor/innen: Annu John, E184 - 4; Igor Konnov, E184 - 4; Ulrich Schmid, E182 - 2; Helmut Veith, E184 - 4; Josef Widder, E184 - 4

    A. John, I. Konnov, U. Schmid, V. Veith, J. Widder:
    "Parameterized model checking of fault-tolerant distributed algorithms by abstraction";
    Vortrag: International Conference on Formal Methods in Computer-Aided Design (FMCAD), Portland, OR, USA; 20.10.2013 - 23.10.2013; in: "FMCAD", (2013), ISBN: 978-0-9835678-3-7; S. 201 - 209.

  275. Autor/innen: Annu John, E184 - 4; Igor Konnov, E184 - 4; Ulrich Schmid, E182 - 2; Helmut Veith, E184 - 4; Josef Widder, E184 - 4

    A. John, I. Konnov, U. Schmid, V. Veith, J. Widder:
    "Towards Modeling and Model Checking Fault-Tolerant Distributed Algorithms";
    Vortrag: International SPIN Symposium on Model Checking of Software (SPIN), Stony Brook, NY, USA; 08.07.2013 - 09.07.2013; in: "SPIN", LNCS, Springer, 7976 (2013), ISBN: 978-3-642-39175-0; S. 209 - 226.

    Zusätzliche Informationen

  276. Autor/in: Albrecht Kadlec, E182 - 1

    A. Kadlec:
    "Neutralizing Timing Anomalies in Superscalar Microprocessors";
    Poster: Junior Scientist Conference 2008, Wien; 16.11.2008 - 18.11.2008; in: "Proceedings of the Junior Scientist Conference 2008", (2008), ISBN: 978-3-200-01612-5; S. 119 - 120.

    Zusätzliche Informationen

  277. Autor/innen: Albrecht Kadlec, E182 - 1; Raimund Kirner, E182 - 1

    A. Kadlec, R. Kirner:
    "On the Difficulty of Building a Precise Timing Model for Real-Time Programming";
    Vortrag: 14. Kolloquium "Programmiersprachen und Grundlagen der Programmierung (KPS'07)", Timmendorfer Strand, Germany; 10.10.2007 - 12.10.2007; in: "14. Kolloquium Programmiersprachen und Grundlagen der Programmierung", (2007), 7 S.

    Zusätzliche Informationen

  278. Autor/innen: Albrecht Kadlec, E182 - 1; Raimund Kirner, E182 - 1; Jens Knoop, E185 - 1; Adrian Prantl, E185 - 1; Markus Schordan, E185 - 1; Ingomar Wenzel, E182 - 1

    A. Kadlec, R. Kirner, J. Knoop, A. Prantl, M. Schordan, I. Wenzel:
    "WCET Annotation Languages Reconsidered: The Annotation Language Challenge";
    Vortrag: 25. Workshop der GI-Fachgruppe "Programmiersprachen und Rechenkonzepte", Bad Honnef; 05.05.2008 - 07.05.2008; in: "Programmiersprachen und Rechenkonzepte", Technischer Bericht des Instituts für Informatik der Christian-Albrechts Universität zu Kiel, 0811 / Kiel (2008), 10 S.

    Zusätzliche Informationen

  279. Autor/innen: Albrecht Kadlec, E182 - 1; Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    A. Kadlec, R. Kirner, P. Puschner:
    "Avoiding Timing Anomalies Using Code Transformations";
    Vortrag: Proceedings of 13th IEEE International Symposium on Object/component/service-oriented Real-time distributed computing (ISORC'10), Carmona, Seville, Spein; 05.05.2010 - 06.05.2010; in: "Avoiding Timing Anomalies Using Code Transformations", IEEE, (2010), ISBN: 978-1-4244-7083-9; S. 123 - 132.

    Zusätzliche Informationen

  280. Autor/innen: Albrecht Kadlec, E182 - 1; Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1; Adrian Prantl, E185 - 1; Markus Schordan, E185 - 1; Jens Knoop, E185 - 1

    A. Kadlec, R. Kirner, P. Puschner, A. Prantl, M. Schordan, J. Knoop:
    "Towards a Common WCET Annotation Language: Essential Ingredients";
    Vortrag: 25. Workshop der GI-Fachgruppe "Programmiersprachen und Rechenkonzepte", Bad Honnef; 05.05.2008 - 07.05.2008; in: "Programmiersprachen und Rechenkonzepte", Technischer Bericht des Instituts für Informatik der Christian-Albrechts Universität zu Kiel, 0811 / Kiel (2008), 12 S.

    Zusätzliche Informationen

  281. Autor/innen: Kenan Kalajdzic, E182 - 1; Ezio Bartocci, E182 - 1; Scott D. Stoller, Stony Brook U; Scott A. Smolka, Stony Brook U; Radu Grosu, E182 - 1

    K. Kalajdzic, E. Bartocci, S. Stoller, S. Smolka, R. Grosu:
    "Runtime Verification with Particle Filtering";
    Vortrag: RV 2013, the Fourth International Conference on Runtime Verification, RENNES, France; 24.09.2013 - 27.09.2013; in: "Proc. of RV 2013, the Fourth International Conference on Runtime Verification", LNCS/Springer, 8174 (2013), ISBN: 978-3-642-40786-4; S. 149 - 166.

    Zusätzliche Informationen

  282. Autor/innen: Kenan Kalajdzic, E182 - 1; Cyrille Jegourel; Axel Legay; Ezio Bartocci, E182 - 1; Anna Lukina, E182 - 1; Scott A. Smolka, Stony Brook U; Radu Grosu, E182 - 1

    K. Kalajdzic, C. Jegourel, A. Legay, E. Bartocci, A. Lukina, S. Smolka, R. Grosu:
    "Model Checking as Control: Feedback Control for Statistical Model Checking of Cyber-Physical Systems";
    Vortrag: Leveraging Applications of Formal Methods, Verification and Validation: Foundational Techniques - 7th International Symposium, ISoLA 2016, Imperial, Corfu, Greece, October 10-14, 2016, Proceedings, Part I, Corfú, Greece; 10.10.2016 - 14.10.2016; in: "Leveraging Applications of Formal Methods, Verification and Validation: Foundational Techniques - 7th International Symposium, ISoLA 2016, Imperial, Corfu, Greece, October 10-14, 2016, Proceedings, Part I", Springer International Publishing, 9952 (2016), ISBN: 978-3-319-47166-2; S. 46 - 61.

    Zusätzliche Informationen

  283. Autor/innen: Roland Kammerer, E182 - 1; Bernhard Frömel, E182 - 1; Roman Obermaisser, Universität Siegen; Paul Milbredt

    R. Kammerer, B. Frömel, R. Obermaisser, P. Milbredt:
    "Composability and Compositionality in CAN-Based Automotive Systems based on Bus and Star Topologies";
    Vortrag: IEEE 11th International Conference on Industrial Informatics INDIN´2013, Bochum, Germany; 29.07.2013 - 31.07.2013; in: "Proceedings of the 11th International Conference on Industrial Informatics INDIN2013", (2013), S. 116 - 122.

    Zusätzliche Informationen

  284. Autor/innen: Roland Kammerer, E182 - 1; Bernhard Frömel, E182 - 1; Armin Wasicek, E182 - 1

    R. Kammerer, B. Frömel, A. Wasicek:
    "Enhancing Security in CAN Systems using a Star Coupling Router";
    Vortrag: 7th IEEE International Symposium on Industrial Embedded Systems (SIES'12), Karlsruhe; 20.06.2012 - 22.06.2012; in: "Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)", IEEE, (2012), ISBN: 978-1-4673-2685-8; S. 237 - 246.

    Zusätzliche Informationen

  285. Autor/innen: Roland Kammerer, E182 - 1; Roman Obermaisser, Universität Siegen; Bernhard Frömel, E182 - 1

    R. Kammerer, R. Obermaisser, B. Frömel:
    "Dynamic Configuration of a Time-Triggered Router for Controller Area Network";
    Vortrag: 17th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), Krakow, Poland; 17.09.2012 - 21.09.2012; in: "17th IEEE International Conference on Emerging Technologies and Factory Automation", (2012).

    Zusätzliche Informationen

  286. Autor/in: Susanne Kandl, E182 - 1

    S. Kandl:
    "Abstraction Techniques for Extracted Automata Models";
    Vortrag: International Conference on Real-Time and Network Systems (RTNS), Nancy; 29.03.2007 - 30.03.2007; in: "Junior Researcher Workshop on Real-Time Computing 2007 (JRWRTC´07)", (2007), S. 35 - 38.

    Zusätzliche Informationen

  287. Autor/in: Susanne Kandl, E182 - 1

    S. Kandl:
    "Cost Effectiveness of Coverage-Guided Test-Suite Reduction for Safety-Relevant Systems";
    Vortrag: Twenty-Third International Conference on Systems Engineering (ICSEng 2014), Las Vegas, Nevada, USA; 19.08.2014 - 21.08.2014; in: "Proceedings of the Twenty-Third International Conference on Systems Engineering (ICSEng 2014)", (2014).

    Zusätzliche Informationen

  288. Autor/in: Susanne Kandl, E182 - 1

    S. Kandl:
    "How Mutations Can Help to Prove That Your System Does Not Contain (Unwanted) Mutations";
    Vortrag: Design, Automation and Test in Europe Conference (DATE), Grenoble, France (eingeladen); 09.03.2015 - 13.03.2015; in: "DATE 2015 - M04 Embedded Systems: Functional Qualification: Applications in the C/C++ Domain", (2015).

    Zusätzliche Informationen

  289. Autor/innen: Susanne Kandl, E182 - 1; Sandeep Chandrashekar

    S. Kandl, S. Chandrashekar:
    "Reasonability of MC/DC for Safety-Relevant Software Implemented in Programming Languages with Short-Circuit Evaluation";
    Vortrag: 9th Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2013), Paderborn, Deutschland; 17.06.2013 - 18.06.2013; in: "Proceedings of the 9th Workshop on Software Technologies for Future Embedded and Ubiquitous Systems", IEEE Proceedings, (2013).

    Zusätzliche Informationen

  290. Autor/innen: Susanne Kandl, E182 - 1; Martin Elshuber, E182 - 1

    S. Kandl, M. Elshuber:
    "A Formal Approach to System Integration Testing";
    Vortrag: Tenth European Dependable Computing Conference (EDCC 2014), Newcastle upon Tyne, UK; 13.05.2014 - 16.05.2014; in: "Proceedings of the Tenth European Dependable Computing Conference (EDCC 2014)", (2014).

    Zusätzliche Informationen

  291. Autor/in: Susanne Kandl, E182 - 1
    Andere beteiligte Personen: Mike Parson; Tom Anderson

    S. Kandl et al.:
    "Applicability of Formal Methods for Safety-Critical Systems in the Context of ISO 26262";
    Vortrag: Safety-critical Systems Symposium (SSS 2015), Bristol, UK; 03.02.2015 - 05.02.2015; in: "Engineering Systems for Safety: Proceedings of the Twenty-third Safety-critical Systems Symposium", M. Parson, T. Anderson (Hrg.); (2015), ISBN: 978-1505689082; S. 95 - 115.

    Zusätzliche Informationen

  292. Autor/innen: Susanne Kandl, E182 - 1; Jean-Marc Forey

    S. Kandl, J. Forey:
    "Fault-Detection Sensitivity Based Assessment of Test Sets for Safety-Relevant Software (Best Paper Award)";
    Vortrag: Seventh International Conference on Dependability (DEPEND 2014), Lisbon, Portugal; 16.11.2014 - 20.11.2014; in: "Proceedings of the Seventh International Conference on Dependability (DEPEND 2014)", (2014), ISBN: 978-1-61208-378-0.

    Zusätzliche Informationen

  293. Autor/innen: Susanne Kandl, E182 - 1; Raimund Kirner, E182 - 1

    S. Kandl, R. Kirner:
    "Error Detection Rate of MC/DC for a Case Study from the Automotive Domain";
    Vortrag: 8th IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems, Waidhofen/Ybbs, Austria; 13.10.2010 - 15.10.2010; in: "Software Technologies for Embedded and Ubiquitous Systems", Lecture Notes in Computer Science, Volume 6399 (2010), S. 131 - 142.

    Zusätzliche Informationen

  294. Autor/innen: Susanne Kandl, E182 - 1; Raimund Kirner, E182 - 1

    S. Kandl, R. Kirner:
    "Systematic Automated Testing of Safety-Critical Applications in the Automotive Domain (Best Poster Award)";
    Vortrag: Junior Scientist Conference, Wien; 19.04.2006 - 21.04.2006; in: "Proceedings of the Junior Scientist Conference 2006", (2006).

    Zusätzliche Informationen

  295. Autor/innen: Susanne Kandl, E182 - 1; Raimund Kirner, E182 - 1; Gordon Fraser

    S. Kandl, R. Kirner, G. Fraser:
    "Verification of Platform-Independent and Platform-Specific Semantics of Dependable Embedded Systems";
    Vortrag: 3rd International Workshop on Dependable Embedded Systems, Leeds, UK; 01.10.2006; in: "3rd International Workshop on Dependable Embedded Systems, Proceedings", (2006), S. 17 - 21.

    Zusätzliche Informationen

  296. Autor/innen: Susanne Kandl, E182 - 1; Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    S. Kandl, R. Kirner, P. Puschner:
    "Automated Formal Verification and Testing of C Programs for Embedded Systems";
    Vortrag: The Tenth IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC 2007), Santorini, Greece; 07.05.2007 - 09.05.2007; in: "10th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2007)", IEEE, (2007), ISBN: 0-7695-2765-5; S. 373 - 381.

    Zusätzliche Informationen

  297. Autor/innen: Susanne Kandl, E182 - 1; Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    S. Kandl, R. Kirner, P. Puschner:
    "Development of a Framework for Automated Systematic Testing of Safety-Critical Embedded Systems";
    Vortrag: 4th Workshop on Intelligent Solutions in Embedded Systems - (WISES06), Vienna, Austria; 30.06.2006; in: "4th Workshop on Intelligent Solutions in Embedded Systems (WISES'06), Proceedings of the", (2006).

    Zusätzliche Informationen

  298. Autor/innen: Wolfgang Kastner, E183 - 1; Bernd Thallner, E182 - 2

    W. Kastner, B. Thallner:
    "A General Public License Linux Device Driver for the EIB";
    Vortrag: EIB Scientific Conference and Technology Workshop, Munich, Germany; 04.10.2001 - 05.10.2001; in: "EIB-Proceedings V", (2001).

  299. Autor/innen: Wolfgang Kastner, E183 - 1; Bernd Thallner, E182 - 2

    W. Kastner, B. Thallner:
    "Connecting EIB to Linux and Java";
    Vortrag: 6th IEEE Africon Conference, George, South Africa; 04.10.2002; in: "Proceedings of the IEEE 6th AFRICON Conference", (2002), ISBN: 0-7803-7570-x; S. 273 - 276.

  300. Autor/innen: Guenter Khyo, E182 - 1; Peter Puschner, E182 - 1; Martin Delvai, E182 - 2

    G. Khyo, P. Puschner, M. Delvai:
    "An Operating System for a Time-Predictable Computing Node";
    Vortrag: The 6th IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2008), Capri, Italien; 01.10.2008 - 03.10.2008; in: "Software Technologies for Embedded and Ubiquitous Systems", Lecture Notes in Computer Science / Springer Verlag, 5287 (2008), ISBN: 978-3-540-87784-4; S. 150 - 161.

    Zusätzliche Informationen

  301. Autor/innen: Kane Kim; Wilfred Recker; W. T. Tsai; Hermann Kopetz, E182 - 1; Peter Puschner, E182 - 1

    K. Kim, W. Recker, W. T. Tsai, H. Kopetz, P. Puschner:
    "DECOS-TADE Collaboration";
    Vortrag: Workshop on the Collaboration between FP6/ISTand NSF/ITR Projects, Ljubljana, Slovenia; 20.10.2005; in: "IST-NSF Workshop on Transatlantic Research Agenda on Future Challenges in Embedded Systems Design", Information Society Technologies/National Science Foundation, (2005), 7 S.

  302. Autor/innen: Attila Kinali; Florian Huemer, E182 - 2; Christoph Lenzen

    A. Kinali, F. Huemer, C. Lenzen:
    "Fault-tolerant Clock Synchronization with High Precision";
    Vortrag: 2016 IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, USA; 11.07.2016 - 13.07.2016; in: "Proc. 2016 IEEE Computer Society Annual Symposium on VLSI", (2016), S. 490 - 495.

    Zusätzliche Informationen

  303. Autor/in: Raimund Kirner, E182 - 1

    R. Kirner:
    "Enforcing Composability for Ubiquitious Computing Systems";
    Vortrag: The Cabernet Radicals Workshop, Bertinoro, Italy; 01.10.2002; in: "Proceedings of the 7th Cabernet Radicals Workshop", (2002).

    Zusätzliche Informationen

  304. Autor/in: Raimund Kirner, E182 - 1

    R. Kirner:
    "On the Halting Problem of Finite-State Programs";
    Vortrag: 14. Kolloquium "Programmiersprachen und Grundlagen der Programmierung (KPS'07)", Timmendorfer Strand, Germany; 10.10.2007 - 12.10.2007; in: "14. Kolloquium Programmiersprachen und Grundlagen der Programmierung", (2007), 6 S.

    Zusätzliche Informationen

  305. Autor/in: Raimund Kirner, E182 - 1

    R. Kirner:
    "SCCP/x - A Compilation Profile to Support Testing and Verification of Optimized Code";
    Vortrag: International Conference on Compilers, Architecture and Synthesis for Embedded Systems [CASES 07], Salzburg, Austria; 30.09.2007 - 05.10.2007; in: "Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems", ACM, (2007), ISBN: 978-1-59593-826-8; S. 38 - 42.

    Zusätzliche Informationen

  306. Autor/in: Raimund Kirner, E182 - 1

    R. Kirner:
    "Towards Automatic Verification of Structural Code-Coverage Preservation";
    Vortrag: Timing Analysis and Symbolic Computation, TASCo 2009, Wien; 04.02.2009 - 05.02.2009; in: "Timing Analysis and Symbolic Computation, TASCo 2009", (2009), 1 S.

    Zusätzliche Informationen

  307. Autor/innen: Raimund Kirner, E182 - 1; Markus Grössing; Peter Puschner, E182 - 1

    R. Kirner, M. Grössing, P. Puschner:
    "Comparing WCET and Resource Demands of Trigonometric Functions Implemented as Iterative Calculations vs. Table-Lookup";
    Poster: Euromicro International Workshop on WCET Analysis, Dresden, Germany; 04.07.2006; in: "6th Euromicro International Workshop on Worst-Case Execution-Time Analysis (WCET), Proceedings of the", (2006), S. 11 - 16.

    Zusätzliche Informationen

  308. Autor/innen: Raimund Kirner, E182 - 1; Walter Haas
    Andere beteiligte Personen: Jens Knoop, E185 - 1; Adrian Prantl, E185 - 1

    R. Kirner, W. Haas:
    "Automatic Calculation of Coverage Profiles for Coverage-based Testing";
    Vortrag: 15. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS 2009), Maria Taferl; 12.10.2009 - 14.10.2009; in: "15. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS 2009)", J. Knoop, A. Prantl (Hrg.); Schriftenreihe des Instituts für Computersprachen, TU Wien, Bericht 2009-X-1 (2009), S. 126 - 140.

    Zusätzliche Informationen

  309. Autor/innen: Raimund Kirner, E182 - 1; Albrecht Kadlec, E182 - 1; Peter Puschner, E182 - 1

    R. Kirner, A. Kadlec, P. Puschner:
    "Precise Worst-Case Execution Time Analysis for Processors with Timing Anomalies";
    Vortrag: Euromicro Conference on Real-Time Systems (ECRTS), Dublin, Ireland; 01.07.2009 - 03.07.2009; in: "Proceedings of The 21th Euromicro Conference on Real-Time Systems", IEEE computer society, CPS, (2009), ISBN: 978-0-7695-3724-5; S. 119 - 128.

    Zusätzliche Informationen

  310. Autor/innen: Raimund Kirner, E182 - 1; Albrecht Kadlec, E182 - 1; Peter Puschner, E182 - 1; Adrian Prantl, E185 - 1; Markus Schordan, E185 - 1; Jens Knoop, E185 - 1

    R. Kirner, A. Kadlec, P. Puschner, A. Prantl, M. Schordan, J. Knoop:
    "Towards a Common WCET Annotation Languge: Essential Ingredients";
    Vortrag: WCET 2008, Prague, Czech Republic; 01.07.2008; in: "Worst-Case Execution Time Analysis; Proceedings of the 8th International Workshop (WCET 2008)", Österreichische Computer Gesellschaft, (2008), ISBN: 978-3-85403-237-3; S. 53 - 65.

    Zusätzliche Informationen

  311. Autor/innen: Raimund Kirner, E182 - 1; Jens Knoop, E185 - 1; Adrian Prantl, E185 - 1; Markus Schordan, E185 - 1; Ingomar Wenzel, E182 - 1

    R. Kirner, J. Knoop, A. Prantl, M. Schordan, I. Wenzel:
    "WCET Analysis: The Annotation Language Challenge";
    Vortrag: 7th International Workshop on Worst-Case Execution Time Analysis (satellite event to ECRTS´07), Pisa, Italy; 03.07.2007; in: "Post-Workshop Proceedings of the 7th International Workshop on Worst-Case Execution Time Analysis", (2007), S. 83 - 99.

    Zusätzliche Informationen

  312. Autor/innen: Raimund Kirner, E182 - 1; Jens Knoop, E185 - 1; Adrian Prantl, E185 - 1; Markus Schordan, E185 - 1; Ingomar Wenzel, E182 - 1

    R. Kirner, J. Knoop, A. Prantl, M. Schordan, I. Wenzel:
    "WCET Analysis: The Annotation Language Challenge";
    Vortrag: 7th International Workshop on Worst-Case Execution Time Analysis (satellite event to ECRTS´07), Pisa; 14.12.2007; in: "Preliminary Proceedings of the 7th International Workshop on Worst-Case Execution Time Analysis (satellite event to ECRTS´07)", (2007), S. 77 - 92.

  313. Autor/innen: Raimund Kirner, E182 - 1; Roland Lang, E182 - 1; Gerald Freiberger; Peter Puschner, E182 - 1

    R. Kirner, R. Lang, G. Freiberger, P. Puschner:
    "Fully Automatic Worst-Case Execution Time Analysis for Matlab/Simulink Models";
    Vortrag: Euromicro Conference on Real-Time Systems (ECRTS), Vienna, Austria; 01.06.2002; in: "Proceedings of the 14th Euromicro International Conference on Real-Time Systems (ECRTS'02)", (2002), S. 31 - 40.

    Zusätzliche Informationen

  314. Autor/innen: Raimund Kirner, E182 - 1; Roland Lang, E182 - 1; Peter Puschner, E182 - 1

    R. Kirner, R. Lang, P. Puschner:
    "WCET Analysis for Systems Modelled in Matlab/Simulink";
    Vortrag: IEEE Real-Time Systems Symposium, London, United Kingdom; 01.12.2001; in: "Proceedings of the IEEE Real-Time Systems Symposium - Work in Progress Proceedings", (2001), S. 33 - 36.

    Zusätzliche Informationen

  315. Autor/innen: Raimund Kirner, E182 - 1; Roland Lang, E182 - 1; Peter Puschner, E182 - 1; Christopher Temple, E182 - 1

    R. Kirner, R. Lang, P. Puschner, C. Temple:
    "Integrating WCET Analysis into a Matlab/Simulink Simulation Model";
    Vortrag: IFAC Workshop on Distributed Computer Control Systems, Sydney, Australia; 29.11.2000 - 01.12.2000; in: "Proceedings of the 16th IFAC Workshop on Distributed Computer Control Systems", (2000), S. 79 - 84.

    Zusätzliche Informationen

  316. Autor/innen: Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1
    Andere beteiligte Person: Wilfried Elmenreich, E182 - 1

    R. Kirner, P. Puschner:
    "A Simple and Effective Fully Automatic Worst-Case Execution-Time Analysis for Model-Based Application Development";
    Vortrag: Workshop on Intelligent Solutions in Embedded Systems, Vienna, Austria; 27.06.2003; in: "Proceedings of the First Workshop on Intelligent Solutions in Embedded Systems", W. Elmenreich (Hrg.); (2003), S. 15 - 24.

    Zusätzliche Informationen

  317. Autor/innen: Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    R. Kirner, P. Puschner:
    "Classification of WCET Analysis Techniques";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Seattle, Washington; 18.05.2005 - 20.05.2005; in: "Proceedings of the 8th IEEE International Symposium on Object-Oriented Real-time distributed Computing (ISORC'05)", IEEE Computer Society, (2005), ISBN: 0-7695-2356-0; S. 190 - 199.

    Zusätzliche Informationen

  318. Autor/innen: Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    R. Kirner, P. Puschner:
    "Consideration of Optimizing Compilers in the Context of WCET Analysis";
    Vortrag: Specialized Informatics Congress, Gesellschaft für Informatik e.V., Bad Schussenried, Germany; 27.10.2000 - 28.10.2000; in: "Proceedings of the Informatiktage 2000, Gesellschaft für Informatik e.V.", (2000), S. 123 - 126.

    Zusätzliche Informationen

  319. Autor/innen: Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    R. Kirner, P. Puschner:
    "Discussion of Misconceptions about Worst-Case Execution-Time Analysis";
    Vortrag: 3rd Euromicro International Workshop on WCET Analysis, Porto, Portugal; 01.07.2003; in: "Proceedings of the 3rd Euromicro International Workshop on WCET Analysis", (2003), S. 61 - 64.

    Zusätzliche Informationen

  320. Autor/innen: Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    R. Kirner, P. Puschner:
    "Obstacles in Worst-Case Execution Time Analysis";
    Vortrag: The 11th IEEE Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, Orlando, Florida, USA; 05.05.2008 - 07.05.2008; in: "The 11th IEEE Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing", IEEE Computer Society, (2008), ISBN: 978-0-7695-3132-8; S. 333 - 339.

    Zusätzliche Informationen

  321. Autor/innen: Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    R. Kirner, P. Puschner:
    "Supporting Control-Flow-Dependent Execution Times on WCET Calculation";
    Vortrag: Deutschsprachige WCET-Tagung, Paderborn, Germany; 20.10.2000; in: "Proceedings of the WCET2000 (Deutschsprachige WCET-Tagung)", (2000), S. #.

    Zusätzliche Informationen

  322. Autor/innen: Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    R. Kirner, P. Puschner:
    "Time-Predictable Computing";
    Vortrag: 8th IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems, Waidhofen/Ybbs, Austria; 13.10.2010 - 15.10.2010; in: "Time-Predictable Computing", (2010), S. 23 - 34.

    Zusätzliche Informationen

  323. Autor/innen: Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    R. Kirner, P. Puschner:
    "Time-Predictable Task Preemption for Real-Time Systems with Direct-Mapped Instruction Cache";
    Vortrag: The Tenth IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC 2007), Santorini, Greece; 07.05.2007 - 09.05.2007; in: "10th IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC'07)", IEEE, (2007), ISBN: 0-7695-2765-5; S. 87 - 92.

    Zusätzliche Informationen

  324. Autor/innen: Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    R. Kirner, P. Puschner:
    "Timing Analysis of Optimised Code";
    Vortrag: IEEE International Workshop on Object-Oriented Real-Time Dependable Systems, Guadalajara, Mexico; 15.01.2003 - 17.01.2003; in: "Proceedings of the 8th International Workshop on Object-Oriented Real-Time Dependable Systems", (2003), S. 100 - 105.

    Zusätzliche Informationen

  325. Autor/innen: Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    R. Kirner, P. Puschner:
    "Transformation of Meta-Information by Abstract Co-Interpretation";
    Vortrag: 7th International Workshop, SCOPES, Vienna, Austria; 24.09.2003 - 26.09.2003; in: "Proceedings of the 7th International Workshop, SCOPES 2003", (2003), S. 298 - 312.

    Zusätzliche Informationen

  326. Autor/innen: Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1

    R. Kirner, P. Puschner:
    "Transformation of Path Information for WCET Analysis during Compilation";
    Vortrag: Euromicro Conference on Real-Time Systems (ECRTS), Delft, Netherlands; 01.06.2001; in: "Proceedings of the 13th Euromicro Conference on Real-Time Systems (ECRTS2001)", (2001), S. 29 - 36.

    Zusätzliche Informationen

  327. Autor/innen: Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1; Ingomar Wenzel, E182 - 1

    R. Kirner, P. Puschner, I. Wenzel:
    "Measurement-Based Worst-Case Execution Time Analysis using Automatic Test-Data Generation";
    Vortrag: Euromicro International Workshop on WCET Analysis, Catania, Italy; 29.07.2004; in: "Proceedings of the", (2004), ISSN: 1166-8687; S. 1 - 4.

    Zusätzliche Informationen

  328. Autor/innen: Raimund Kirner, E182 - 1; Peter Puschner, E182 - 1; Ingomar Wenzel, E182 - 1; Bernhard Rieder, E182 - 1

    R. Kirner, P. Puschner, I. Wenzel, B. Rieder:
    "Portable Data Exchange for Remote-Testing Frameworks";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Gyeongju, Korea; 24.04.2006 - 26.04.2006; in: "Proceedings of the Ninth IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing", IEEE, (2006), ISBN: 0-7695-2561-x.

    Zusätzliche Informationen

  329. Autor/innen: Raimund Kirner, E182 - 1; Christian Scheidler; Günter Grünsteidl, E182 - 1; Ulrich Virnich; Samuel Boutin; Jörn Rennhack; Roland Lang, E182 - 1; Manfred Pisecky; Yiannis Papadopoulos

    R. Kirner, C. Scheidler, G. Grünsteidl, U. Virnich, S. Boutin, J. Rennhack, R. Lang, M. Pisecky, Y. Papadopoulos:
    "Systems Engineering von zeitgesteuerten Systemen - das SETTA Prozessmodell";
    Vortrag: VDI/VDE GMA Fachtagung, Steuerung und Regelung von Fahrzeugen und Motoren, Mannheim, Deutschland; 15.04.2002 - 16.04.2002; in: "Tagungsband der VDI/VDE GMA Fachtagung, Steuerung und Regelung von Fahrzeugen und Motoren - AutoReg ", (2002), S. 662 - 676.

    Zusätzliche Informationen

  330. Autor/innen: Raimund Kirner, E182 - 1; Martin Schoeberl, E182 - 1

    R. Kirner, M. Schoeberl:
    "Modeling the function cache for worst-case execution time analysis";
    Vortrag: 44th Design Automation Conference (DAC'07), San Diego, California/USA; 04.06.2007 - 08.06.2007; in: "Proceedings of the 44th annual conference on Design automation", ACM, (2007), ISBN: 978-1-59593-627-1; S. 471 - 476.

    Zusätzliche Informationen

  331. Autor/innen: Raimund Kirner, E182 - 1; Wolf Zimmermann; Dirk Richter
    Andere beteiligte Personen: Jens Knoop, E185 - 1; Adrian Prantl, E185 - 1

    R. Kirner, W. Zimmermann, D. Richter:
    "On Undecidability Results of Real Programming Languages";
    Vortrag: 15. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS 2009), Maria Taferl; 12.10.2009 - 14.10.2009; in: "15. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS 2009)", J. Knoop, A. Prantl (Hrg.); Schriftenreihe des Instituts für Computersprachen, TU Wien, Bericht 2009-X-1 (2009), S. 141 - 154.

    Zusätzliche Informationen

  332. Autor/innen: Raimund Kirner, E182 - 1; Michael Zolda, E182 - 1

    R. Kirner, M. Zolda:
    "Compiler Support for Measurement-based Timing Analysis";
    Vortrag: 11th International Workshop on Worst-Case Execution-Time Analysis, Porto, Portugal (eingeladen); 05.07.2011; in: "Proceedings of the 11th International Workshop on Worst-Case Execution Time (WCET) Analysis", (2011), S. 62 - 71.

    Zusätzliche Informationen

  333. Autor/innen: Gernot Klingler, E182 - 1; Alexander Kößler, E182 - 1; Wilfried Elmenreich, E182 - 1

    G. Klingler, A. Kößler, W. Elmenreich:
    "The Smart Car - a distributed controlled autonomous robot";
    Vortrag: Junior Scientist Conference, Vienna, Austria; 19.04.2006 - 21.04.2006; in: "Proceedings of the Junior Scientist Conference 2006", (2006), ISBN: 3-902463-05-8; S. 33 - 34.

    Zusätzliche Informationen

  334. Autor/innen: Alexander Kößler, E182 - 1; Wilfried Elmenreich, E182 - 1

    A. Kößler, W. Elmenreich:
    "Automated solution evaluation during a practical examination";
    Vortrag: Junior Scientist Conference, Vienna, Austria; 19.04.2006 - 21.04.2006; in: "Proceedings of the Junior Scientist Conference 2006", (2006), ISBN: 3-902463-05-8; S. 35 - 36.

    Zusätzliche Informationen

  335. Autor/innen: Alexander Kößler, E182 - 2; Heinrich Moser, E182 - 2; Ulrich Schmid, E182 - 2

    A. Kößler, H. Moser, U. Schmid:
    "Real-Time Analysis of Round-based Distributed Algorithms";
    Vortrag: RTSOPS 2010 (1st International Real-Time Scheduling Open Problems Seminar), Brussels, Belgium; 06.07.2010 - 09.07.2010; in: "Proceedings of the 1st International Real-Time Scheduling Open Problems Seminar", (2010), S. 9 - 11.

    Zusätzliche Informationen

  336. Autor/innen: Hui Kong; Ezio Bartocci, E182 - 1; Sergiy Bogomolov, Univ. Freiburg; Radu Grosu, E182 - 1; Thomas A. Henzinger; Yu Jiang; Christian Schilling

    H. Kong, E. Bartocci, S. Bogomolov, R. Grosu, T. Henzinger, Y. Jiang, C. Schilling:
    "Discrete Abstraction of Multiaffine Systems";
    Vortrag: Hybrid Systems Biology - 5th International Workshop, HSB 2016, Grenoble, France, October 20-21, 2016, Proceedings, Grenoble, France; 20.10.2016 - 21.10.2016; in: "Hybrid Systems Biology - 5th International Workshop, HSB 2016, Grenoble, France, October 20-21, 2016, Proceedings", Springer International Publishing, 9957 (2016), ISBN: 978-3-319-47151-8; S. 128 - 144.

    Zusätzliche Informationen

  337. Autor/innen: Igor Konnov, E184 - 4; Marijana Lazić, E184 - 4; Helmut Veith, E184 - 4; Josef Widder, E182 - 2

    I. Konnov, M. Lazić, V. Veith, J. Widder:
    "A short counterexample property for safety and liveness verification of fault-tolerant distributed algorithms";
    Vortrag: 44th ACM SIGPLAN Symposium on Principles of Programming Languages (POPL), Paris, France; 18.01.2017 - 20.01.2017; in: "POPL", ACM, Paris (2017), ISBN: 978-1-4503-4660-3; S. 719 - 734.

    Zusätzliche Informationen

  338. Autor/innen: Igor Konnov, E184 - 4; Helmut Veith, E184 - 4; Josef Widder, E182 - 2

    I. Konnov, V. Veith, J. Widder:
    "SMT and POR beat Counter Abstraction: Parameterized Model Checking of Threshold-Based Distributed Algorithms";
    Vortrag: International Conference on Computer Aided Verification (CAV), San Francisco, CA, USA; 18.07.2015 - 24.07.2015; in: "Computer Aided Verification", LNCS Springer, 9206 (2015), ISBN: 978-3-319-21689-8; S. 85 - 102.

    Zusätzliche Informationen

  339. Autor/innen: Igor Konnov, E184 - 4; Helmut Veith, E184 - 4; Josef Widder, E182 - 2

    I. Konnov, V. Veith, J. Widder:
    "What You Always Wanted to Know About Model Checking of Fault-Tolerant Distributed Algorithms";
    Hauptvortrag: Perspectives of System Informatics: 10th International Andrei Ershov Informatics Conference, Kazan, Russland (eingeladen); 25.08.2015 - 27.08.2015; in: "Perspectives of System Informatics: 10th International Andrei Ershov Informatics Conference, PSI 2015", LNCS / Springer, 9609 (2016), S. 6 - 21.

    Zusätzliche Informationen

  340. Autor/innen: Igor Konnov, E184 - 4; Josef Widder, E182 - 2; Francesco Spegni, UnivPM; Luca Spalazzi, UnivPM

    I. Konnov, J. Widder, F. Spegni, L. Spalazzi:
    "Accuracy of Message Counting Abstraction in Fault-Tolerant Distributed Algorithms";
    Vortrag: Verification, Model Checking, and Abstract Interpretation (VMCAI), Paris; 15.01.2017 - 17.01.2017; in: "VMCAI 2017: Verification, Model Checking, and Abstract Interpretation", Springer, LNCS/10145/Paris (2017), ISBN: 978-3-319-52233-3; S. 347 - 366.

    Zusätzliche Informationen

  341. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "A Conceptual Model for the Information Transfer in System of Systems";
    Vortrag: 17th IEEE International Symposium on Object/Component-Oriented Real-Time Distributed Computing (ISORC), Reno, Nevada, USA; 08.06.2014 - 12.06.2014; in: "Proc. of the 17th IEEE International Symposium on Object/Component-Oriented Real-Time Distributed Computing", (2014), ISSN: 1555-0885; S. 17 - 24.

    Zusätzliche Informationen

  342. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "A Universal Smart Transducer Interface";
    Vortrag: V Simpósio Brasileiro de Automação Inteligente, Canela, Brasilien; 07.11.2001 - 09.11.2001; in: "Proceedings of the V Simpósio Brasileiro de Automação Inteligente", (2001), S. 1 - 8.

    Zusätzliche Informationen

  343. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "An integrated architecture for dependable embedded systems";
    Vortrag: IEEE Symposium on Reliable Distributed Systems, Florianopolis, Brazil (eingeladen); 18.10.2004 - 20.10.2004; in: "Proceedings of the 23rd IEEE International Symposium on Reliable Distributed Systems, 2004. ", IEEE, (2004), S. 160 - 161.

  344. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "Composability in the Time-Triggered Architecture";
    Vortrag: SAE International Congress and Exhibition, Detroit, USA; 06.03.2000 - 09.03.2000; in: "Proceedings of the SAE International Congress and Exhibition (2000-01-1382)", (2000), S. #.

    Zusätzliche Informationen

  345. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "Composability in the time-triggered system-on-chip architecture";
    Vortrag: Proceedings of the 21st Annual IEEE International SoC Conference, Vienna, Austria; 28.08.2008 - 30.08.2008; in: "Proceedings of the 21st Annual IEEE International SoC Conference", (2008), ISBN: 978-1-4244-2596-9; S. 87 - 90.

    Zusätzliche Informationen

  346. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "Composable Embedded Systems";
    Vortrag: IEEE International Conference on Computational Cybernetics, Vienna, Autria; 30.08.2004 - 01.09.2004; in: "Proceedings of the IEEE International Conference on Computational Cybernetics (ICCC 2004)", IEEE, (2004), ISBN: 3-902463-01-5; S. 3.

  347. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "Composition of component services";
    Vortrag: IEEE International Workshop on Object-Oriented Real-Time Dependable Systems, Vienna, Austria (eingeladen); 12.05.2004 - 14.05.2004; in: "Proceedings of the Seventh IEEE International Symposium on Object-Oriented Real-Time Distributed Computing, 2004. (ISORC)", IEEE, (2004), ISBN: 0-7695-2124-x; S. 3.

  348. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "Modeling of Software-Hardware Complexes";
    Vortrag: International Embedded Systems Symposiom (IESS'07), Irvine, Orange County, in Southern California (USA); 30.05.2007 - 01.06.2007; in: "Embedded System Design: Topics, Techniques and Trends", Springer Boston, Volume 231/2007 (2007), ISBN: 978-0-387-72257-3; S. 431 - 432.

    Zusätzliche Informationen

  349. Autor/in: Hermann Kopetz, E182 - 1
    Andere beteiligte Person: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "On the Fault Hypothesis for a Safety-Critical Real-Time System";
    Vortrag: Future Generation Software Architectures in the Automotive Domain, San Diego, USA (eingeladen); 10.01.2004 - 12.01.2004; in: "On the Fault Hypothesis for a Safety-Critical Real-Time System", H. Kopetz (Hrg.); (2004).

    Zusätzliche Informationen

  350. Autor/in: Hermann Kopetz, E182 - 1
    Andere beteiligte Personen: Bernd Kleinjohann; Lisa Kleinjohann; Ricardo J. Machado; Carlos Pereira; P.S. Thiagarajan

    H. Kopetz:
    "Pulsed Data Streams";
    Vortrag: IFIP Working Conference on Distributed and Parallel Embedded Systems, Braga, Portugal (eingeladen); 11.10.2006 - 13.10.2006; in: "5th IFIP Working Conference on Distributed and Parallel Embedded Systems, Proceedings", B. Kleinjohann, L. Kleinjohann, R.J. Machado, C. Pereira, P. Thiagarajan (Hrg.); Springer, (2006), ISBN: 0-387-39361-7; S. 105 - 114.

  351. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "Simplification Principles in the Design of Cyber-Physical System-of-Systems";
    Vortrag: Sixth International Conference on Complex Systems Design & Management, CSD&M 2015, Paris (eingeladen); 23.11.2015 - 25.11.2015; in: "Complex Systems Design & Management", Springer International Publishing, (2015), ISBN: 978-3-319-26109-6; S. 39 - 51.

  352. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "Software Engineering for Real-Time: A Roadmap";
    Vortrag: International Conference on Future of Software Engineering, Limerick, Ireland; 04.06.2000 - 11.06.2000; in: "Proceedings of the 22nd International conference on Future of Software Engineering (FoSE)", (2000), S. #.

    Zusätzliche Informationen

  353. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "The Complexity Challenge in Embedded System Design";
    Vortrag: The 11th IEEE Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, Orlando, Florida, USA; 05.05.2008 - 07.05.2008; in: "The 11th IEEE Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing", IEEE Computer Society, (2008), ISBN: 978-0-7695-3132-8; S. 3 - 12.

    Zusätzliche Informationen

  354. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "The Temporal Specification of Interfaces in Distributed Real-Time Systems";
    Vortrag: International Workshop on Embedded Software, Lake Tahoe, CA, USA; 08.10.2001 - 10.10.2001; in: "Proceedings of the EMSOFT", (2001), S. 223 - 236.

    Zusätzliche Informationen

  355. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "The Three Interfaces of a Smart Transducer";
    Vortrag: IFAC International Conference on Fieldbus Systems and their Applications, Nancy, France; 15.11.2001 - 16.11.2001; in: "Proceedings of the FeT`2001 - 4th IFAC International Conference on Fieldbus Systems and their Applications", (2001).

    Zusätzliche Informationen

  356. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "Time-Triggered Real-Time Computing";
    Vortrag: IFAC World Congress, Barcelona, Portugal; 21.07.2002 - 26.07.2002; in: "Proceedings of the IFAC World Congress", IFAC Press, (2002).

    Zusätzliche Informationen

  357. Autor/in: Hermann Kopetz, E182 - 1
    Andere beteiligte Personen: Miroslav Malek; Edgar Nett; Neeraj Suri

    H. Kopetz:
    "TTA Supported Service Availability";
    Hauptvortrag: International Service Availability Symposium, Berlin, Germany (eingeladen); 25.04.2005 - 26.04.2005; in: "Service Availability - Second International Availability Symposium", M. Malek, E. Nett, N. Suri (Hrg.); Springer, LNCS 3694 (2005), ISBN: 3-540-29103-2; S. 1 - 14.

    Zusätzliche Informationen

  358. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "Why do we need a Sparse Global Time-Base in Dependable Real-time Systems?";
    Vortrag: 2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication, Vienna; 01.10.2007 - 03.10.2007; in: "ISPCS Proceedings", (2007), ISBN: 1-4244-1064-9; Paper-Nr. 03 (Session 1/3), 5 S.

    Zusätzliche Informationen

  359. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "Wrong Assumptions and Neglected Areas in Embedded Systems Research";
    Vortrag: The 11th IEEE Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, Orlando, Florida, USA; 05.05.2008 - 07.05.2008; in: "The 11th IEEE Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing", IEEE Computer Society, (2008), ISBN: 978-0-7695-3132-8; S. 360.

  360. Autor/in: Hermann Kopetz, E182 - 1

    H. Kopetz:
    "Zuverlässige Elektronik-Systeme im Verkehrswesen";
    Vortrag: Conference of the Academy of Science of Northrhine - Westfalia, Northrhine - Westfalia, Germany; 13.12.2006; in: "Informatik bewegt - Informationstechnik in Verkehr und Logistik", acatech, (2007), ISBN: 978-3-8167-7368-9; S. 55 - 79.

  361. Autor/innen: Hermann Kopetz, E182 - 1; Astrit Ademaj, E182 - 1; Petr Grillinger, E182 - 1; Klaus Steinhammer, E182 - 1

    H. Kopetz, A. Ademaj, P. Grillinger, K. Steinhammer:
    "The Time-Triggered Ethernet (TTE) Design";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Seattle, Washington; 18.05.2005 - 20.05.2005; in: "Proceedings of the 8th IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC)", IEEE Computer Society, (2005), ISBN: 0-7695-2356-0; S. 22 - 33.

    Zusätzliche Informationen

  362. Autor/innen: Hermann Kopetz, E182 - 1; Astrit Ademaj, E182 - 1; Alexander Hanzlik, E182 - 1

    H. Kopetz, A. Ademaj, A. Hanzlik:
    "Integration of Internal and External Clock Synchronization by the Combination of Clock-State and Clock-Rate Correction in Fault-Tolerant Distributed Systems";
    Vortrag: IEEE Real-Time Systems Symposium, Lisbon, Portugal; 05.12.2004 - 08.12.2004; in: "Proceedings of the 25th IEEE International Real-Time Systems Symposium", IEEE, (2004), ISBN: 0-7695-2247-5.

    Zusätzliche Informationen

  363. Autor/innen: Hermann Kopetz, E182 - 1; Günther Bauer, E182 - 1; Stefan Poledna, E182 - 1

    H. Kopetz, G. Bauer, S. Poledna:
    "Tolerating Arbitrary Node Failures in the Time-Triggered Architecture";
    Vortrag: SAE World Congress, Detroit, MI, USA; 01.03.2001; in: "Proceedings of the SAE 2001 World Congress", (2001).

    Zusätzliche Informationen

  364. Autor/innen: Hermann Kopetz, E182 - 1; Wilfried Elmenreich, E182 - 1; Christoph Mack

    H. Kopetz, W. Elmenreich, C. Mack:
    "A Comparison of LIN and TTP/A";
    Vortrag: IEEE International Workshop on Factory Communication Systems, Porto, Portugal; 06.09.2000 - 08.09.2000; in: "Proceedings of the 3rd IEEE International Workshop on Factory Communication Systems (WFCS 2000)", (2000), S. 99 - 107.

    Zusätzliche Informationen

  365. Autor/innen: Hermann Kopetz, E182 - 1; Bernhard Frömel, E182 - 1; Oliver Höftberger, E182 - 1

    H. Kopetz, B. Frömel, O. Höftberger:
    "Direct versus Stigmergic Information Flow in Systems-of-Systems";
    Vortrag: 10th Annual Systems of Systems Engineering Conference 2015, San Antonio, TX, USA; 17.05.2015 - 20.05.2015; in: "10th Annual Systems of Systems Engineering Conference 2015", (2015), S. 36 - 41.

    Zusätzliche Informationen

  366. Autor/innen: Hermann Kopetz, E182 - 1; Oliver Höftberger, E182 - 1; Bernhard Frömel, E182 - 1; Francesco Brancati, Resiltech S.R.L.; Andrea Bondavalli, UNIFI

    H. Kopetz, O. Höftberger, B. Frömel, F. Brancati, A. Bondavalli:
    "Towards an Understanding of Emergence in Systems-of-Systems";
    Vortrag: 10th Annual Systems of Systems Engineering Conference 2015, San Antonio, TX, USA; 17.05.2015 - 20.05.2015; in: "10th Annual Systems of Systems Engineering Conference 2015", (2015), S. 214 - 219.

    Zusätzliche Informationen

  367. Autor/innen: Hermann Kopetz, E182 - 1; Michael Holzmann, E182 - 1; Wilfried Elmenreich, E182 - 1

    H. Kopetz, M. Holzmann, W. Elmenreich:
    "A Universal Smart Transducer Interface: TTP/A";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Newport Beach, CA, USA; 15.03.2000 - 17.03.2000; in: "Proceedings of the third IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC 2000)", (2000).

    Zusätzliche Informationen

  368. Autor/innen: Hermann Kopetz, E182 - 1; Roman Obermaisser, Universität Siegen; Christian El Salloum, E182 - 1; Bernhard Huber, E182 - 1

    H. Kopetz, R. Obermaisser, C. El Salloum, B. Huber:
    "Automotive Software Development for a Multi-Core System-on-a-Chip";
    Vortrag: SEAS'07, Minneapolis, USA; 26.05.2007; in: "Fourth International Workshop on Software Engineering for Automotive Systems", IEEE, (2007), ISBN: 978-84-89315-47-1; S. 101 - 113.

    Zusätzliche Informationen

  369. Autor/innen: Hermann Kopetz, E182 - 1; Neeraj Suri

    H. Kopetz, N. Suri:
    "Compositional Design of RT Systems: A Conceptual Basis for Specification of Linking Interfaces";
    Vortrag: 6th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC'03), Hokkaido, Japan; 14.05.2003 - 16.05.2003; in: "Proceedings of the 6th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC'03)", (2003), S. 1 - 10.

    Zusätzliche Informationen

  370. Autor/innen: Stephan Korsholm, AAU; Martin Schoeberl, E182 - 1; Anders P. Ravn, Denmark

    S. Korsholm, M. Schoeberl, A. Ravn:
    "Interrupt Handlers in Java";
    Vortrag: The 11th IEEE Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, Orlando, Florida, USA; 05.05.2008 - 07.05.2008; in: "The 11th IEEE Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing", IEEE Computer Society, (2008), ISBN: 978-0-7695-3132-8; S. 453 - 457.

    Zusätzliche Informationen

  371. Autor/innen: Thomas Kottke; Andreas Steininger, E182 - 2

    T. Kottke, A. Steininger:
    "A Dual Core Architecture with Error Containment";
    Vortrag: East-West Design & Test International Workshop(EWDTW´04), Yalta-Alushta, Crimea, Ukraine; 23.09.2004 - 26.09.2004; in: "East-West Design & Test International Workshop", (2004), ISBN: 966-659-088-3; S. 102 - 108.

    Zusätzliche Informationen

  372. Autor/innen: Thomas Kottke; Andreas Steininger, E182 - 2

    T. Kottke, A. Steininger:
    "A Fail-Silent Reconfigurable Superscalar Processor";
    Vortrag: 13th Pacific Rim International Symposium on Dependable Computing (PRDC 07), Melbourne; 17.12.2007 - 19.12.2007; in: "13th Pacific Rim International Symposium on Dependable Computing (PRDC'07), Melbourne", (2007), S. 232 - 239.

    Zusätzliche Informationen

  373. Autor/innen: Thomas Kottke; Andreas Steininger, E182 - 2

    T. Kottke, A. Steininger:
    "A Generic Dual-Core Architecture";
    Vortrag: 7th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2004), Stara Lesna, Slovakia; 18.04.2004 - 21.04.2004; in: "7th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2004)", (2004), ISBN: 80-969117-9-1; S. 159 - 166.

    Zusätzliche Informationen

  374. Autor/innen: Thomas Kottke; Andreas Steininger, E182 - 2

    T. Kottke, A. Steininger:
    "A Reconfigurable Generic Dual-Core Architecture";
    Vortrag: IEEE International Conference on Dependable Systems and Networks, Philadelphia; 25.06.2006 - 28.06.2006; in: "Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN)", (2006), S. 45 - 54.

    Zusätzliche Informationen

  375. Autor/innen: Thomas Kottke; Andreas Steininger, E182 - 2

    T. Kottke, A. Steininger:
    "Designoptimierung eines Prozessors mit Eigenfehlererkennung";
    Vortrag: 17. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen;, Inssbruck; 27.02.2005 - 01.03.2005; in: "16. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen;", (2005), S. 55 - 59.

    Zusätzliche Informationen

  376. Autor/innen: Thomas Kottke; Andreas Steininger, E182 - 2

    T. Kottke, A. Steininger:
    "Vergleich zweier zwischen Sicherheit und Performanz rekonfigurierbarer Prozessorsysteme";
    Poster: 19. ITG/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Errlangen; 11.03.2007 - 13.03.2007; in: "19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (2007).

  377. Autor/innen: Stefan Viktor Krywult; Wilfried Elmenreich, E182 - 1

    S. V. Krywult, W. Elmenreich:
    "A Portable Real-Time Communication System for Embedded Systems with Heterogeneous Hardware";
    Vortrag: Junior Scientist Conference, Vienna, Austria; 19.04.2006 - 21.04.2006; in: "Proceedings of the Junior Scientist Conference 2006", (2006), ISBN: 3-902463-05-8; S. 41 - 42.

    Zusätzliche Informationen

  378. Autor/in: Sibylle Kuster, E182 - 1

    S. Kuster:
    "Successful communication in European research projects - the GENESYS project as best practice";
    Vortrag: 2. Projekt Management Symposium der Fachhochschule des bfi Wien, Wien; 16.06.2011; in: "Wirtschaft und Management, Schriftenreihe zur Wissenschaftlichen Forschung und Praxis, Band 15", Wirtschaft und Management, Heft 15 (2011), S. 75 - 89.

    Zusätzliche Informationen

  379. Autor/innen: G´erard Le Lann; Ulrich Schmid, E182 - 2

    G. Le Lann, U. Schmid:
    "Proof-Based Systems Engineering in ASSERT";
    Vortrag: Data Systems in Aerospace, Edinburgh; 30.05.2005 - 02.06.2005; in: "Proof-Based Systems Engineering in ASSERT", (2005).

  380. Autor/in: Jakob Lechner, E182 - 2

    J. Lechner:
    "Designing Robust GALS Circuits with Triple Modular Redundancy";
    Vortrag: 2012 European Dependable Computing Conference (EDCC 2012), Sibiu, Romania; 08.05.2012 - 11.05.2012; in: "Dependable Computing Conference (EDCC), 2012 Ninth European", (2012), S. 227 - 236.

    Zusätzliche Informationen

  381. Autor/innen: Jakob Lechner, E182 - 2; Martin Delvai, E182 - 2

    J. Lechner, M. Delvai:
    "Implementation of a Design Tool for Automated Generation of Four State Logic Circuits";
    Poster: Junior Scientist Conference 2008, Wien; 16.11.2008 - 18.11.2008; in: "Proceedings of the Junior Scientist Conference 2008", (2008), ISBN: 978-3-200-01612-5; S. 85 - 86.

  382. Autor/innen: Jakob Lechner, E182 - 2; Martin Lampacher, E182

    J. Lechner, M. Lampacher:
    "Protecting Pipelined Asynchronous Communication Channels Against Single Event Upsets";
    Vortrag: IEEE 30th International Conference on Computer Design (ICCD 2012), Montreal, Canada; 30.09.2012 - 03.10.2012; in: "Computer Design (ICCD), 2012 IEEE 30th International Conference on", (2012), ISSN: 1063-6404; S. 480 - 481.

    Zusätzliche Informationen

  383. Autor/innen: Jakob Lechner, E182 - 2; Martin Lampacher, E182; Thomas Polzer, E182 - 2

    J. Lechner, M. Lampacher, T. Polzer:
    "A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding";
    Vortrag: 2012 International Conference on Application of Concurrency to System Design (ACSD 2012), Hamburg, Germany; 27.06.2012 - 29.06.2012; in: "Application of Concurrency to System Design (ACSD), 2012 12th International Conference on", (2012), ISSN: 1550-4808; S. 122 - 131.

    Zusätzliche Informationen

  384. Autor/innen: Jakob Lechner, E182 - 2; Robert Najvirt, E182 - 2

    J. Lechner, R. Najvirt:
    "A Generic Architecture for Robust Asynchronous Communication Links";
    Poster: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2012, Newcastle upon Tyne; 04.09.2012 - 06.09.2012; in: "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation", Lecture Notes in Computer Science, 7606 (2013), ISBN: 978-3-642-36156-2; S. 121 - 130.

    Zusätzliche Informationen

  385. Autor/innen: Jakob Lechner, E182 - 2; Andreas Steininger, E182 - 2; Florian Huemer, E182 - 2

    J. Lechner, A. Steininger, F. Huemer:
    "Methods for Analysing and Improving the Fault Resilience of Delay-Insensitive Codes";
    Vortrag: 33rd IEEE International Conference on Computer Design, New York City, USA; 19.10.2015 - 21.10.2015; in: "33rd IEEE International Conference on Computer Design", (2015), 8 S.

    Zusätzliche Informationen

  386. Autor/innen: Voin Legourski, E182 - 2; Christian Trödhandl, E182 - 1; Bettina Weiss, E182 - 2

    V. Legourski, C. Trödhandl, B. Weiss:
    "A System for Automatic Testing of Embedded Software in Undergraduate Study Exercises";
    Vortrag: Workshop on Embedded Systems Education, Jersey City; 22.09.2005; in: "Proceedings Workshop on Embedded Systems Education (WESE'05)", (2005), S. 44 - 51.

    Zusätzliche Informationen

  387. Autor/innen: Bernhard Leiner; Martin Schlager; Roman Obermaisser, Universität Siegen; Bernhard Huber, E182 - 1

    B. Leiner, M. Schlager, R. Obermaisser, B. Huber:
    "A Comparison of Partitioning Operating Systems for Integrated Systems";
    Vortrag: SAFECOMP, Nuremberg, Germany; 18.09.2007 - 21.09.2007; in: "Computer Safety, Reliability, and Security", Springer, LNCS Vol 4680 (2007), ISBN: 978-3-540-75100-7; S. 342 - 355.

    Zusätzliche Informationen

  388. Autor/innen: Christoph Lenzen; Matthias Függer, E182 - 2; Martin Hofstätter; Ulrich Schmid, E182 - 2

    C. Lenzen, M Függer, M. Hofstätter, U. Schmid:
    "Efficient Construction of Global Time in SoCs despite Arbitrary Faults";
    Vortrag: 16th Euromicro Conference on Digital System Design (DSD 2013), Santander, Spain; 04.09.2013 - 06.09.2013; in: "Dependable", Digital System Design (DSD), 2013 Euromicro Conference on, (2013), S. 142 - 151.

  389. Autor/in: Thomas Losert, E182 - 1
    Andere beteiligte Person: Wilfried Elmenreich, E182 - 1

    T. Losert:
    "Adding Hard Real-time Capabilities to CORBA";
    Vortrag: Workshop on Intelligent Solutions in Embedded Systems, Vienna, Austria; 27.06.2003; in: "Proceedings of the First Workshop on Intelligent Solutions in Embedded Systems", W. Elmenreich (Hrg.); (2003), S. 57 - 66.

    Zusätzliche Informationen

  390. Autor/innen: Thomas Losert, E182 - 1; Wilfried Elmenreich, E182 - 1; Martin Schlager, E182 - 1

    T. Losert, W. Elmenreich, M. Schlager:
    "Semi-Automatic Compensation of the Propagation-Delay in Fault-Tolerant Systems";
    Vortrag: IASTED International Conference on Communications, Internet, and Information Technology (CIIT 2004), US Virgin Islands; 22.11.2004 - 24.11.2004; in: "Proceedings of the Third International Conference on Communications, Internet, and Information Technology (CIIT 2004)", ACTA Press, (2004), ISBN: 0-88986-445-4; S. 455 - 460.

    Zusätzliche Informationen

  391. Autor/innen: Thomas Losert, E182 - 1; Wolfgang Huber, E182 - 2; Karl Hendling, E389; Martin Jandl, E384

    T. Losert, W. Huber, K. Hendling, M. Jandl:
    "An Extensible Transport Framework for CORBA with Emphasis on Real-Time Capabilities";
    Vortrag: Second IEEE International Conference on Computational Cybernetics 2004 (ICCC'04), Vienna, Austria; 30.08.2004 - 01.09.2004; in: "Proceeding of ICCC'04", (2004), ISBN: 3-902463-01-5; S. 155 - 161.

    Zusätzliche Informationen

  392. Autor/innen: Thomas Losert, E182 - 1; Roman Obermaisser, Universität Siegen

    T. Losert, R. Obermaisser:
    "Wireless Real-Time Communication Technologies: A Comparative Study";
    Vortrag: IEEE Workshop on Real-Time Embedded Systems, London, United Kingdom; 03.12.2001; in: "Proceedings of the IEEE Workshop on Real-Time Embedded Systems", (2001).

    Zusätzliche Informationen

  393. Autor/innen: Anna Lukina, E182 - 1; Lukas Esterle, E182 - 1; Christian Hirsch, E182 - 1; Ezio Bartocci, E182 - 1; Junxing Yang; Scott A. Smolka, Stony Brook U; Ashish Tiwari; Radu Grosu, E182 - 1

    A. Lukina, L. Esterle, C. Hirsch, E. Bartocci, J. Yang, S. Smolka, A. Tiwari, R. Grosu:
    "ARES: Adaptive Receding-Horizon Synthesis of Optimal Plans";
    Vortrag: TACAS 2017: the 23rd International Conference on Tools and Algorithms for the Construction and Analysis of Systems, Uppsala, Sweden; 22.04.2017 - 29.04.2017; in: "Proc. of TACAS 2017: the 23rd International Conference on Tools and Algorithms for the Construction and Analysis of Systems", Springer, 10206 (2017), S. 286 - 302.

  394. Autor/innen: Ramin M. Hasani, E182 - 1; Dieter Haerle; Radu Grosu, E182 - 1

    R. M. Hasani, D. Haerle, R. Grosu:
    "Efficient Modeling of Complex Analog Integrated Circuits Using Neural Networks";
    Vortrag: 12th Conference on PhD Research in Microelectronics and Electronics (PRIME) 2016, Lisbon, Portugal; 27.06.2016 - 30.06.2016; in: "Proc. of PRIME 2016: 12th conference on PhD research on microelectronics and electronics", IEEE, (2016), ISBN: 978-1-5090-0493-5; S. 1 - 4.

    Zusätzliche Informationen

  395. Autor/innen: Jürgen Maier, E182 - 2; Andreas Steininger, E182 - 2

    J. Maier, A. Steininger:
    "Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic";
    Vortrag: 17th Symposium on Design and Diagnosis of Electronic Circuits and Systems (DDECS 2014), Warschau, Polen; 23.04.2014 - 25.04.2014; in: "Design and Diagnostics of Electronic Circuits Systems (DDECS), 2014 IEEE 17th International Symposium on", (2014), 6 S.

    Zusätzliche Informationen

  396. Autor/innen: Oleksandr Melnychenko, E182 - 1; Hans-Peter Kreuter, Infineon

    O. Melnychenko, H.-P. Kreuter:
    "A Metric Driven Verification and Validation Approach for Smart Power Devices";
    Vortrag: 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Villach; 24.06.2013 - 27.06.2013; in: "Conference Proceedings. 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)", (2013), ISBN: 978-1-4673-4580-4; S. 289 - 292.

    Zusätzliche Informationen

  397. Autor/innen: Oleksandr Melnychenko, E182 - 1; Hans-Peter Kreuter, Infineon

    O. Melnychenko, H.-P. Kreuter:
    "Interfacing UVM Test Bench and Laboratory Equipment for Power Devices Verification";
    Vortrag: 21st Austrian Workshop on Microelectronics (Austrochip), Linz; 10.10.2013; in: "Austrochip 2013. Tagungsband", (2013), S. 17 - 21.

    Zusätzliche Informationen

  398. Autor/in: Vaclav Mikolasek, E182 - 1

    V. Mikolasek:
    "Dependability and Robustness: State of the Art and Challenges";
    Vortrag: First International Workshop on Software Technologies for Future Dependable Distributed Systems (STFSSD 2009), Tokyo, Japan; 17.03.2009 - 18.03.2009; in: "2009 Software Technologies for Future Dependable Distributed Systems", IEEE, (2009), ISBN: 978-0-7695-3572-2; S. 25 - 31.

    Zusätzliche Informationen

  399. Autor/innen: Vaclav Mikolasek, E182 - 1; Astrit Ademaj, E182 - 1; Stanislav Racek

    V. Mikolasek, A. Ademaj, S. Racek:
    "Segmentation of Standard Ethernet Messages in the Time-Triggered Ethernet";
    Vortrag: IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), Hamburg, Germany; 15.09.2008 - 18.09.2008; in: "Proceedings of the 13th IEEE International Conference on Emerging Technologies and Factory Automation", IEEE, (2008), ISBN: 1-4244-1506-3; S. 392 - 399.

    Zusätzliche Informationen

  400. Autor/innen: Vaclav Mikolasek, E182 - 1; Hermann Kopetz, E182 - 1

    V. Mikolasek, H. Kopetz:
    "Roll-Forward Recovery with State Estimation";
    Vortrag: 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC 2011), Newport Beach, California, USA; 28.03.2011 - 31.03.2011; in: "14th IEEE International Symposium on Object/Component/Service-oriented Real-time Distributed Computing (ISORC)", IEEE, (2011), ISBN: 978-1-61284-433-6; S. 179 - 186.

    Zusätzliche Informationen

  401. Autor/innen: Paul Milbredt; Michael Glass; Martin Lukasiewycz; Andreas Steininger, E182 - 2; Jürgen Teich

    P. Milbredt, M. Glass, M. Lukasiewycz, A. Steininger, J. Teich:
    "Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach";
    Vortrag: Design, Automation & Test in Europe Conference & Exhibition (DATE 2012), Dresden, Germany; 12.03.2012 - 16.03.2012; in: "Design, Automation & Test in Europe Conference & Exhibition (DATE 2012) Proceedings", EDAA, (2012), ISBN: 978-3-9810801-8-6; S. 276 - 279.

    Zusätzliche Informationen

  402. Autor/innen: Paul Milbredt; Martin Horauer, E384; Andreas Steininger, E182 - 2

    P. Milbredt, M. Horauer, A. Steininger:
    "An Investigation of the Clique Problem in Flex Ray";
    Vortrag: SIES´2008 Third international symposium on industrial embedded systems, Montpellier - La Grande Motte, France; 11.08.2008 - 13.08.2008; in: "International Symposium on Industrial Embedded Systems, 2008.", (2008), ISBN: 978-1-4244-1995-1; S. 200 - 207.

    Zusätzliche Informationen

  403. Autor/innen: Paul Milbredt; Andreas Steininger, E182 - 2; Martin Horauer, E384

    P. Milbredt, A. Steininger, M. Horauer:
    "Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks";
    Vortrag: IEEE International Workshop on Electronic Design, Test and Applications, Hong-Kong; 23.05.2008 - 25.05.2008; in: "4th IEEE International Symposium on Electronic Design, Test and Applications, 2008. DELTA 2008.", (2008), ISBN: 978-0-7695-3110-6; S. 533 - 538.

    Zusätzliche Informationen

  404. Autor/innen: Marco Mori, UNIFI; Andrea Ceccarelli, UNIFI; Paolo Lollini, UNIFI; Andrea Bondavalli, UNIFI; Bernhard Frömel, E182 - 1

    M. Mori, A. Ceccarelli, P. Lollini, A. Bondavalli, B. Frömel:
    "A holistic viewpoint-based SysML Profile to Design Systems-of-Systems";
    als Vortrag angenommen für: 17th IEEE International Symposium on High Assurance Systems Engineering, Orlando, Florida, USA; 07.01.2016 - 09.01.2016; in: "High Assurance Systems Engineering (HASE), 2016 IEEE 17th International Symposium on", (2016), ISSN: 1530-2059; S. 276 - 283.

    Zusätzliche Informationen

  405. Autor/innen: Heinrich Moser, E182 - 2; Ulrich Schmid, E182 - 2

    H. Moser, U. Schmid:
    "Construction of a Fault-Tolerant Wireless Communication Topology Using Distributed Agreement";
    Vortrag: Junior Scientist Conference, Wien; 19.04.2006 - 21.04.2006; in: "Junior Scientiest Conferenve 2006", (2006), S. 47 - 48.

    Zusätzliche Informationen

  406. Autor/innen: Heinrich Moser, E182 - 2; Ulrich Schmid, E182 - 2

    H. Moser, U. Schmid:
    "Optimal clock synchronization revisited: Upper and lower bounds in real-time systems";
    Vortrag: International Conference On Principles Of Distributed Systems (OPODIS), Bordeaux; 12.12.2006 - 14.12.2006; in: "Principles of Distributed Systems", (2006), S. 94 - 109.

    Zusätzliche Informationen

  407. Autor/innen: Heinrich Moser, E182 - 2; Ulrich Schmid, E182 - 2

    H. Moser, U. Schmid:
    "Optimal Deterministic Remote Clock Estimation in Real-Time Systems";
    Vortrag: 12th International Conference On Principles of Distributed Systems, Luxor, Ägypten; 15.12.2008 - 18.12.2008; in: "Principles of Distributed Systems", Lecture Notes in Computer Science / Springer Verlag, Volume 5401 (2008), ISBN: 978-3-540-92220-9; S. 363 - 387.

    Zusätzliche Informationen

  408. Autor/innen: Heinrich Moser, E182 - 2; Ulrich Schmid, E182 - 2

    H. Moser, U. Schmid:
    "Reconciling Fault-Tolerant Distributed Algorithms and Real-Time Computing";
    Vortrag: Structural Information and Communication Complexity, Gdansk; 26.06.2011 - 29.06.2011; in: "Proceedings 18th International Colloquium on Structural Information and Communication Complexity (SIROCCO'11)", Springer Berlin / Heidelberg, (2011), ISBN: 978-3-642-22211-5; S. 42 - 53.

    Zusätzliche Informationen

  409. Autor/innen: Heinrich Moser, E182 - 2; Bernd Thallner, E182 - 2

    H. Moser, B. Thallner:
    "Construction of a Fault-Tolerant Wireless Communication Topology Using Distributed Agreement";
    Vortrag: Workshop on Dependability issues in wireless ad hoc networks and sensor networks (DIWANS), Los Angeles; 25.09.2006; in: "DIWANS '06: Proceedings of the 2006 workshop on Dependability issues in wireless ad hoc networks and sensor networks", (2006), S. 35 - 43.

    Zusätzliche Informationen

  410. Autor/innen: Heinrich Moser, E182 - 2; Bernd Thallner, E182 - 2

    H. Moser, B. Thallner:
    "Reconciling Distributed Computing Models and Real-Time Systems";
    Vortrag: IEEE Real-Time Systems Symposium, Rio de Janiero; 05.12.2006 - 08.12.2006; in: "Proceedings of the 27th IEEE Real-Time Systems Symposium (RTSS'06)", (2006), S. 73 - 76.

    Zusätzliche Informationen

  411. Autor/innen: Abhishek Murthy, Stony Brook U; Islam Ariful, Stony Brook U; Ezio Bartocci, E182 - 1; Elizabeth Cherry, Rochester Inst.; Flavio H. Fenton, Cornell U.; James Glimm, Stony Brook U; Scott A. Smolka, Stony Brook U; Radu Grosu, E182 - 1

    A. Murthy, I. Ariful, E. Bartocci, E. Cherry, F. Fenton, J. Glimm, S. Smolka, R. Grosu:
    "Approximate Bisimulations for Sodium Channel Dynamics";
    Vortrag: The 10th ACM International Conference on Computational Methods in Systems Biology (CMSB 2012), London, UK; 03.10.2012 - 05.10.2012; in: "Proc. of CMSB 2012: the 10th ACM International Conference on Computational Methods in Systems Biology", LNCS / Springer, vol. 7605 (2012), ISBN: 978-3-642-33635-5; S. 267 - 287.

    Zusätzliche Informationen

  412. Autor/innen: Abhishek Murthy, Stony Brook U; Ezio Bartocci, E182 - 1; Flavio H. Fenton, Cornell U.; James Glimm, Stony Brook U; Richard A. Gray, FDA; Scott A. Smolka, Stony Brook U; Radu Grosu, E182 - 1

    A. Murthy, E. Bartocci, F. Fenton, J. Glimm, R. Gray, S. Smolka, R. Grosu:
    "Curvature analysis of cardiac excitation wavefronts";
    Poster: CMSB 2011: the 9th ACM International Conference on Computational Methods in Systems Biology, Paris, France; 21.09.2011 - 23.09.2011; in: "Proc. of CMSB 2011: the 9th ACM International Conference on Computational Methods in Systems Biology", ACM, (2011), ISBN: 978-1-4503-0817-5; S. 103 - 112.

    Zusätzliche Informationen

  413. Autor/innen: Abhishek Murthy, Stony Brook U; Ariful Islam; Scott A. Smolka, Stony Brook U; Radu Grosu, E182 - 1

    A. Murthy, A. Islam, S. Smolka, R. Grosu:
    "Computing Bisimulation Functions using SOS Optimisation and delta-decidability over the Reals";
    Vortrag: 18th International Conference on Hybrid Systems: Computation and Control (HSCC), Seattle, USA; 13.04.2015 - 15.04.2015; in: "HSCC 2015", ACM, (2015), ISBN: 978-1-4503-3433-4; S. 78 - 87.

    Zusätzliche Informationen

  414. Autor/innen: Liana Musat; Markus Hübl; Andi Buzo; Georg Pelz; Susanne Kandl, E182 - 1; Peter Puschner, E182 - 1

    L. Musat, M. Hübl, A. Buzo, G. Pelz, S. Kandl, P. Puschner:
    "Semi-formal Representation of Requirements for Automotive Solutions using SysML";
    Vortrag: Forum on specification & Design Languages (FDL), Munich, Germany; 14.10.2014 - 16.10.2014; in: "Proceedings of the Forum on Specification & Design Languages (FDL 2014)", (2014).

    Zusätzliche Informationen

  415. Autor/innen: Liana Musat; Susanne Kandl, E182 - 1; Peter Puschner, E182 - 1; Markus Hübl; Andi Buzo; Georg Pelz

    L. Musat, S. Kandl, P. Puschner, M. Hübl, A. Buzo, G. Pelz:
    "Requirement Semi-formalization Methodology for SoC Design (Best Paper Award)";
    Vortrag: 12th International SoC Design Conference (ISOCC 2015), Gyeongju, South Korea; 02.11.2015 - 05.11.2015; in: "Proceedings of the 12th International SoC Design Conference (IEEE)", (2015).

    Zusätzliche Informationen

  416. Autor/innen: Robert Najvirt, E182 - 2; Matthias Függer, E182 - 2; Thomas Nowak; Ulrich Schmid, E182 - 2; Michael Hofbauer, E354; Kurt Schweiger, E354

    R. Najvirt, M Függer, T. Nowak, U. Schmid, M. Hofbauer, K. Schweiger:
    "Experimental Validation of a Faithful Binary Circuit Model";
    Vortrag: Great Lakes Symposium on VLSI (GLSVLSI'15), Pittsburgh, Pennsylvania, USA; 2015; in: "Proceedings of the 25th Edition on Great Lakes Symposium on VLSI (GLSVLSI'15)", (2015), ISBN: 978-1-4503-3474-7; S. 355 - 360.

  417. Autor/innen: Robert Najvirt, E182 - 2; Syed Rameez Naqvi, E182 - 2; Andreas Steininger, E182 - 2

    R. Najvirt, S. Naqvi, A. Steininger:
    "Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs";
    Vortrag: 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2013), Santa Monica, CA; 19.05.2013 - 22.05.2013; in: "Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on", (2013), ISSN: 1522-8681; 9 S.

    Zusätzliche Informationen

  418. Autor/innen: Robert Najvirt, E182 - 2; Thomas Polzer, E182 - 2; Florian Beck, E182 - 2; Andreas Steininger, E182 - 2

    R. Najvirt, T. Polzer, F. Beck, A. Steininger:
    "Containment of Metastable Voltages in FPGAs";
    Vortrag: 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Belgrad; 22.04.2015 - 24.04.2015; in: "18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", (2015), 6 S.

    Zusätzliche Informationen

  419. Autor/innen: Robert Najvirt, E182 - 2; Andreas Steininger, E182 - 2

    R. Najvirt, A. Steininger:
    "A Pausible Clock with Crystal Oscillator Accuracy";
    Vortrag: 22nd European Conference on Circuit Theory and Design, Trondheium, Norwegen; 24.08.2015 - 26.08.2015; in: "22nd European Conference on Circuit Theory and Design", (2015), Paper-Nr. 67, 4 S.

    Zusätzliche Informationen

  420. Autor/innen: Robert Najvirt, E182 - 2; Andreas Steininger, E182 - 2

    R. Najvirt, A. Steininger:
    "A Versatile and Reliable Glitch Filter for Clocks";
    Vortrag: 25th International Workshop on Power and Timing Modeling, Optimization and Simulation, Salvador, Brasilien; 01.09.2015 - 04.09.2015; in: "25th International Workshop on Power and Timing Modeling, Optimization and Simulation", (2015), 8 S.

    Zusätzliche Informationen

  421. Autor/innen: Robert Najvirt, E182 - 2; Andreas Steininger, E182 - 2

    R. Najvirt, A. Steininger:
    "Equivalence of Clock Gating and Synchronization with Applicability to GALS Communication";
    Vortrag: 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, Isles Balears, Spain; 29.09.2014 - 01.10.2014; in: "Proceedings of the 24th International Workshop on Power and Timing Modeling, Optimization and Simulation", IEEE, (2014), ISBN: 978-1-4799-5412-4; Paper-Nr. 29, 8 S.

    Zusätzliche Informationen

  422. Autor/innen: Robert Najvirt, E182 - 2; Andreas Steininger, E182 - 2

    R. Najvirt, A. Steininger:
    "How to Synchronize a Pausible Clock to a Reference";
    Vortrag: 21st IEEE International Symposium on Asynchronous Circuits and Systems, Mountain View, CA; 04.05.2015 - 06.05.2015; in: "21st IEEE International Symposium on Asynchronous Circuits and Systems", (2015), 8 S.

    Zusätzliche Informationen

  423. Autor/innen: Robert Najvirt, E182 - 2; Savulimedu Veeravall Varadan, E182 - 2; Andreas Steininger, E182 - 2

    R. Najvirt, S. Varadan, A. Steininger:
    "Particle Strikes in C-Gates: Relevance of SET Shapes";
    Vortrag: 2nd Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale, Avignon; 30.05.2013 - 31.05.2013; in: "Proceedings of the MEDIAN Workshop 2013", (2013), 4 S.

    Zusätzliche Informationen

  424. Autor/in: Syed Rameez Naqvi, E182 - 2

    S. Naqvi:
    "An Asynchronous Router Architecture using Four-Phase Bundled Handshake Protocol";
    Vortrag: ICCGI 2012 : The Seventh International Multi-Conference on Computing in the Global Information Technology, Venice, Italy; 24.06.2012 - 29.06.2012; in: "Proc. of The Seventh International Multi-Conference on Computing in the Global Information Technology", (2012), ISBN: 978-1-61208-202-8; 6 S.

    Zusätzliche Informationen

  425. Autor/innen: Syed Rameez Naqvi, E182 - 2; Jakob Lechner, E182 - 2; Andreas Steininger, E182 - 2

    S. Naqvi, J. Lechner, A. Steininger:
    "Protection of Muller-Pipelines from Transient Faults";
    Vortrag: 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA; 10.03.2014 - 12.03.2014; in: "Proceedings 15th International Symposium & Exhibit on Quality Electronic Design", (2014), ISBN: 978-1-4799-3946-6; 9 S.

    Zusätzliche Informationen

  426. Autor/innen: Syed Rameez Naqvi, E182 - 2; Robert Najvirt, E182 - 2; Andreas Steininger, E182 - 2

    S. Naqvi, R. Najvirt, A. Steininger:
    "A Multi-Credit Flow Control Scheme for Asynchronous NoCs";
    Vortrag: 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Karoly Vary, Czech Republic; 08.04.2013 - 10.04.2013; in: "Proc. 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems", (2013), 6 S.

    Zusätzliche Informationen

  427. Autor/innen: Syed Rameez Naqvi, E182 - 2; Andreas Steininger, E182 - 2

    S. Naqvi, A. Steininger:
    "A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments";
    Vortrag: Design Automation &Test in Europe Conference and Exhibition 2014 (DATE 14), Dresden, Deutschland; 24.03.2014 - 28.03.2014; in: "Proceedings Design Automation &Test in Europe", (2014), ISBN: 978-3-9815370-2-4; 6 S.

    Zusätzliche Informationen

  428. Autor/innen: Syed Rameez Naqvi, E182 - 2; Andreas Steininger, E182 - 2; Jakob Lechner, E182 - 2

    S. Naqvi, A. Steininger, J. Lechner:
    "An SET Tolerant Tree Arbiter Cell";
    Vortrag: 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2013), Santa Monica, CA; 19.05.2013 - 22.05.2013; in: "Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on", (2013), ISSN: 1522-8681; 9 S.

    Zusätzliche Informationen

  429. Autor/innen: Syed Rameez Naqvi, E182 - 2; Savulimedu Veeravall Varadan, E182 - 2; Andreas Steininger, E182 - 2

    S. Naqvi, S. Varadan, A. Steininger:
    "Protecting an Asynchronous NoC against Transient Channel Faults";
    Vortrag: DSD 2012 (Euromicro Conference on Digital System Design), Cesme, Izmir, Turkey; 05.09.2012 - 08.09.2012; in: "Proc. of 15th Euromicro Conference on Digital System Design", (2012), 8 S.

    Zusätzliche Informationen

  430. Autor/innen: Thang Nguyen; Ezio Bartocci, E182 - 1; Dejan Nickovic, AIT; Radu Grosu, E182 - 1; Stefan Jaksic; Konstantin Selyunin, E182 - 1

    T. Nguyen, E. Bartocci, D. Nickovic, R. Grosu, S. Jaksic, K. Selyunin:
    "The HARMONIA project: Hardware Monitoring for Automotive Systems-of-Systems";
    Vortrag: Leveraging Applications of Formal Methods, Verification and Validation: Foundational Techniques - 7th International Symposium, ISoLA 2016, Imperial, Corfu, Greece, October 10-14, 2016, Proceedings, Part I, Corfú, Greece (eingeladen); 10.10.2016 - 14.10.2016; in: "Leveraging Applications of Formal Methods, Verification and Validation: Foundational Techniques - 7th International Symposium, ISoLA 2016, Imperial, Corfu, Greece, October 10-14, 2016, Proceedings, Part I", Springer International Publishing, 9952 (2016), ISBN: 978-3-319-47166-2; S. 371 - 379.

  431. Autor/innen: Thomas Nowak; Matthias Függer, E182 - 2; Alexander Kößler, E182 - 2

    T. Nowak, M Függer, A. Kößler:
    "On the Performance of a Retransmission-Based Synchronizer";
    Vortrag: Structural Information and Communication Complexity, Gdansk; 26.06.2011 - 29.06.2011; in: "Structural Information and Communication Complexity", Springer Berlin / Heidelberg, (2011), ISBN: 978-3-642-22211-5; S. 234 - 245.

    Zusätzliche Informationen

  432. Autor/innen: Roman Obermaisser, Universität Siegen; Christian El Salloum, E182 - 1; Bernhard Huber, E182 - 1; Hermann Kopetz, E182 - 1

    R. Obermaisser, C. El Salloum, B. Huber, H. Kopetz:
    "Fundamental Design Principles for Embedded Systems: The Architectural Style of the Cross-Domain Architecture GENESYS";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Tokyo, Japan; 17.03.2009 - 20.03.2009; in: "12th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing", IEEE, (2009), S. 3 - 11.

    Zusätzliche Informationen

  433. Autor/innen: Roman Obermaisser, Universität Siegen; Christian El Salloum, E182 - 1; Bernhard Huber, E182 - 1; Hermann Kopetz, E182 - 1

    R. Obermaisser, C. El Salloum, B. Huber, H. Kopetz:
    "The Time-Triggered System-on-a-Chip Architecture";
    Vortrag: IEEE International Symposium on Industrial Electronics, 2008. ISIE 2008, Cambridge, UK; 30.06.2008 - 02.07.2008; in: "IEEE International Symposium on Industrial Electronics, 2008. ISIE 2008", (2008), ISBN: 978-1-4244-1666-0; S. 1941 - 1947.

    Zusätzliche Informationen

  434. Autor/innen: Roman Obermaisser, Universität Siegen; Bernhard Frömel, E182 - 1; Christian El Salloum, E182 - 1; Bernhard Huber, E182 - 1

    R. Obermaisser, B. Frömel, C. El Salloum, B. Huber:
    "Integrating safety and multimedia subsystems on a Time-Triggered System-on-a-Chip";
    Vortrag: Proceedings IEEE INDIN 2008, 6th IEEE International Conference on Industrial Informatics, Daejeon, Korea; 13.07.2008 - 16.07.2008; in: "Proceedings IEEE INDIN 2008, 6th IEEE International Conference on Industrial Informatics", IEEE, (2008), ISBN: 978-1-4244-2171-8; S. 270 - 275.

    Zusätzliche Informationen

  435. Autor/innen: Roman Obermaisser, Universität Siegen; Emmanuel Henrich; Kane Kim; Hermann Kopetz, E182 - 1; Moo Hwan Kim

    R. Obermaisser, E. Henrich, K. Kim, H. Kopetz, M. H. Kim:
    "Integration of two Complementary Time-Triggered Technologies: TMO and TTP";
    Vortrag: International Embedded Systems Symposium, Manaus, Brazil; 15.08.2005 - 17.08.2005; in: "Proceedings of the International Embedded Systems Symposium 2005", Springer, (2005), ISBN: 0-387-27557-6; S. 1 - 12.

    Zusätzliche Informationen

  436. Autor/innen: Roman Obermaisser, Universität Siegen; Oliver Höftberger, E182 - 1

    R. Obermaisser, O. Höftberger:
    "Fault Containment in a Reconfigurable Multi‐Processor System‐on‐a‐Chip";
    Vortrag: 21st IEEE International Symposium on Industrial Electronics (ISIE 2011), Gdansk, Poland; 27.06.2011 - 30.06.2011; in: "21st IEEE International Symposium on Industrial Electronics (ISIE 2011", IEEE, (2011), ISBN: 978-1-4244-9312-8; S. 1561 - 1568.

    Zusätzliche Informationen

  437. Autor/innen: Roman Obermaisser, Universität Siegen; Bernhard Huber, E182 - 1

    R. Obermaisser, B. Huber:
    "Model-Based Design of the Communication System in an Integrated Architecture";
    Vortrag: International Conference on Parallel and and Distributed Computing and Systems (PDCS), Dallas, Texas, USA; 13.11.2006 - 15.11.2006; in: "International Conference on Parallel and Distributed Computing and Systems (PDCS 2006), Proceedings of the", (2006).

    Zusätzliche Informationen

  438. Autor/innen: Roman Obermaisser, Universität Siegen; Roland Kammerer, E182 - 1

    R. Obermaisser, R. Kammerer:
    "A Router for Improved Fault Isolation, Scalability and Diagnosis in CAN";
    Vortrag: IEEE International Conference on Industrial Informatics (INDIN 2010), Osaka, Japan; 13.07.2010 - 16.07.2010; in: "A Router for Improved Fault Isolation, Scalability and Diagnosis in CAN", (2010), S. 121 - 127.

    Zusätzliche Informationen

  439. Autor/innen: Roman Obermaisser, Universität Siegen; Roland Kammerer, E182 - 1; Andreas Kasper

    R. Obermaisser, R. Kammerer, A. Kasper:
    "Sternkoppler für Controller Area Network (CAN) auf Basis eines Multi-Processor System-on-a-Chip (MPSoC)";
    Vortrag: AmE 2011 - Automotive meets Electronics, Dortmund, Deutschland (eingeladen); 04.05.2011 - 05.05.2011; in: "Proc. of AmE 2011 - Automotive meets Electronics", (2011).

    Zusätzliche Informationen

  440. Autor/innen: Roman Obermaisser, Universität Siegen; Hermann Kopetz, E182 - 1; Christian El Salloum, E182 - 1; Bernhard Huber, E182 - 1

    R. Obermaisser, H. Kopetz, C. El Salloum, B. Huber:
    "Error Containment in the Time-Triggered System-On-a-Chip Architecture";
    Vortrag: International Embedded Systems Symposiom (IESS'07), Irvine, Orange County, in Southern California (USA); 30.05.2007 - 01.06.2007; in: "Embedded System Design: Topics, Techniques and Trends", Springer Boston, Volume 231/2007 (2007), ISBN: 978-0-387-72257-3; S. 339 - 352.

    Zusätzliche Informationen

  441. Autor/innen: Roman Obermaisser, Universität Siegen; Hubert Kraut, E182 - 1; Christian El Salloum, E182 - 1

    R. Obermaisser, H. Kraut, C. El Salloum:
    "A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR";
    Vortrag: Seventh European Dependable Computing Conference (EDCC-7), Kaunas, Lithuania; 07.05.2008 - 09.05.2008; in: "Seventh European Dependable Computing Conference (EDCC-7)", IEEE Computer Society, (2008), ISBN: 978-0-7695-3138-0; S. 123 - 134.

    Zusätzliche Informationen

  442. Autor/innen: Roman Obermaisser, Universität Siegen; Jon Perez; Christian El Salloum, E182 - 1; Carlos Fernando Nicolas

    R. Obermaisser, J. Perez, C. El Salloum, Carlos Nicolas:
    "Modeling Time-Triggered Architecture Based Safety-Critical Embedded Systems Using SystemC";
    Vortrag: Forum on specification & Design Languages (FDL), Southampton, UK; 14.09.2010 - 16.09.2010; in: "Modeling Time-Triggered Architecture Based Safety-Critical Embedded Systems Using SystemC", (2010).

    Zusätzliche Informationen

  443. Autor/innen: Roman Obermaisser, Universität Siegen; Philipp Peti, E182 - 1

    R. Obermaisser, P. Peti:
    "A Fault Hypothesis for Integrated Architectures";
    Vortrag: 4th Workshop on Intelligent Solutions in Embedded Systems - (WISES06), Vienna, Austria; 30.06.2006; in: "Fourth Workshop on Intelligent Solutions in Embedded Systems - WISES06", (2006), ISBN: 3-902463-06-6; S. 47 - 54.

    Zusätzliche Informationen

  444. Autor/innen: Roman Obermaisser, Universität Siegen; Philipp Peti, E182 - 1

    R. Obermaisser, P. Peti:
    "Detection of Out-of-Norm Behaviors in Event-Triggered Virtual Networks";
    Vortrag: IEEE International Conference on Industrial Informatics - INDIN 2007, Vienna, Austria; 23.07.2007 - 27.07.2007; in: "5th IEEE International Conference on Industrial Informatics (INDIN 2007)", IEEE, VOL2 (2007), ISBN: 978-1-4244-0851-1; S. 971 - 976.

    Zusätzliche Informationen

  445. Autor/innen: Roman Obermaisser, Universität Siegen; Philipp Peti, E182 - 1

    R. Obermaisser, P. Peti:
    "Specification and Execution of Gateways in Integrated Architectures";
    Vortrag: ETFA, Catania, Italy; 19.09.2005 - 22.09.2005; in: "Proceedings of the 10th IEEE Internationla Conference on Emerging Technologies and Factory Automation", IEEE, II (2005), ISBN: 0-7803-9402-x; S. 689 - 698.

    Zusätzliche Informationen

  446. Autor/innen: Roman Obermaisser, Universität Siegen; Philipp Peti, E182 - 1

    R. Obermaisser, P. Peti:
    "The Fault Assumptions in Distributed Integrated Architectures";
    Vortrag: SAE 2007 AeroTech Congress & Exhibition, Los Angeles, California, USA; 17.09.2007 - 20.09.2007; in: "Aerospace Safety- Design, Maintenance/Operations, and Safety/Security", SAE, SP-2141 (2007), ISBN: 978-0-7680-1961-2.

    Zusätzliche Informationen

  447. Autor/innen: Roman Obermaisser, Universität Siegen; Philipp Peti, E182 - 1; Wilfried Elmenreich, E182 - 1; Thomas Losert, E182 - 1

    R. Obermaisser, P. Peti, W. Elmenreich, T. Losert:
    "Monitoring and Configuration in a Smart Transducer Network";
    Vortrag: IEEE Workshop on Real-Time Embedded Systems, London, United Kingdom; 03.12.2001; in: "Proceedings of the IEEE Workshop on Real-Time Embedded Systems", (2001).

    Zusätzliche Informationen

  448. Autor/innen: Roman Obermaisser, Universität Siegen; Philipp Peti, E182 - 1; Hermann Kopetz, E182 - 1

    R. Obermaisser, P. Peti, H. Kopetz:
    "Virtual Gateways in the DECOS Integrated Architecture";
    Vortrag: Workshop on Parallel and Distributed Real-Time Systems (WPDRTS), Denver, Colorado; 04.04.2005 - 08.04.2005; in: "Proceedings of the 13th Workshop on Parallel and Distributed Real-Time Systems 2005 (WPDRTS)", (2005), ISBN: 0-7695-2312-9.

    Zusätzliche Informationen

  449. Autor/innen: Roman Obermaisser, Universität Siegen; Philipp Peti, E182 - 1; Hermann Kopetz, E182 - 1

    R. Obermaisser, P. Peti, H. Kopetz:
    "Virtual Networks in an Integrated Time-Triggered Architecture";
    Vortrag: IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS), Sedona, Arizona; 02.02.2005 - 04.02.2005; in: "Proceedings of the 10th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems, 2005", (2005).

    Zusätzliche Informationen

  450. Autor/innen: Roman Obermaisser, Universität Siegen; Dominique Riezler, E182 - 1

    R. Obermaisser, D. Riezler:
    "HIS/VectorCAN Driver API on Top of a Time-Triggered Communication Protocol";
    Vortrag: SAE World Congress & Exhibition, Detroit, MI, USA; 16.04.2007 - 19.04.2007; in: "Proc. of the SAE World Congress & Exhibition", SAE, In-Vehicle Networks, 2007 - SP-2102 (2007), ISBN: 978-0-7680-1892-9.

    Zusätzliche Informationen

  451. Autor/innen: Roman Pallierer, E182 - 1; Martin Horauer; Andreas Steininger, E182 - 2

    R. Pallierer, M. Horauer, A. Steininger:
    "Monitoring and Fault Injection of X-by-Wire Communication Networks";
    Vortrag: Entwicklerforum Design & Elektronik: Drahtlose und drahtgebundene Netzwerke, Wien; 03.02.2004; in: "Entwicklerforum Design & Elektronik: Drahtlose und drahtgebundene Netzwerke", (2004).

    Zusätzliche Informationen

  452. Autor/innen: Thomas Panhofer; Werner Friesenbichler, Austrian Aerospace; Martin Delvai, E182 - 2

    T. Panhofer, W. Friesenbichler, M. Delvai:
    "Fault Tolerant Four-State Logic by Using Self-Healing Cells";
    Vortrag: 2008 IEEE International Conference on Computer Design, Lake Tahoe, CA, USA; 12.10.2008 - 15.10.2008; in: "2008 IEEE International Conference on Computer Design", IEEE, (2008), ISBN: 978-1-4244-2658-4; 6 S.

    Zusätzliche Informationen

  453. Autor/innen: Christian Paukovits, E182 - 1; Wilfried Elmenreich, E182 - 1

    C. Paukovits, W. Elmenreich:
    "Meta-Modelling in Tool Support for Time-Triggered Application Development";
    Vortrag: Junior Scientist Conference, Vienna, Austria; 19.04.2006 - 21.04.2006; in: "Proceedings of the Junior Scientist Conference 2006", (2006), ISBN: 3-902463-05-8; S. 53 - 54.

    Zusätzliche Informationen

  454. Autor/innen: Christian Paukovits, E182 - 1; Hermann Kopetz, E182 - 1

    C. Paukovits, H. Kopetz:
    "Concepts of Switching in the Time-Triggered Network-on-Chip";
    Vortrag: 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2008), Kaohsiung, Taiwan; 25.08.2008 - 27.08.2008; in: "14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications", IEEE Computer Society, (2008), ISSN: 1533-2306; S. 120 - 129.

    Zusätzliche Informationen

  455. Autor/innen: Harald Paulitsch, E182 - 1; Roman Obermaisser, Universität Siegen; Christian El Salloum, E182 - 1; Bernhard Huber, E182 - 1; Hermann Kopetz, E182 - 1

    H. Paulitsch, R. Obermaisser, C. El Salloum, B. Huber, H. Kopetz:
    "A Diagnostic Unit for the time-triggered System-on-a-Chip architecture";
    Poster: Design, Automation and Test in Europe Conference (DATE'07), Nice, France; 16.04.2007 - 20.04.2007; in: "Workshop Digest, Diagnostic Services in Network-on-Chips", DATE'07, (2007), Paper-Nr. ? (Seite 387f), 2 S.

    Zusätzliche Informationen

  456. Autor/innen: Harald Paulitsch, E182 - 1; Christian Paukovits, E182 - 1; Christian El Salloum, E182 - 1

    H. Paulitsch, C. Paukovits, C. El Salloum:
    "Fault Isolation with Intermediate Checks of End-to-end Checksums in the Time-Triggered System-on-Chip Architecture";
    Vortrag: 2009 IEEE International Symposium on Industrial Embedded Systems, SIES 2009 Proceedings, Lausanne, Switzerland; 08.07.2009 - 10.07.2009; in: "Industrial Embedded Systems, 2009. SIES '09. IEEE International Symposium on", IEEE, (2009), ISBN: 978-1-4244-4110-5; S. 90 - 99.

    Zusätzliche Informationen

  457. Autor/innen: Michael Paulitsch, E182 - 1; Wilfried Steiner, E182 - 1

    M. Paulitsch, W. Steiner:
    "Fault-Tolerant Clock Synchronization for Embedded Distributed Multi-Cluster Systems";
    Vortrag: 15th Euromicro Conference on Real-Time Systems, Porto, Portugal; 02.07.2003 - 04.07.2003; in: "Proceedings of the 15th Euromicro Conference on Real-Time Systems", (2003), S. 249 - 256.

    Zusätzliche Informationen

  458. Autor/innen: Andreas Pavlogiannis, IST; Krishnendu Chatterjee; Ulrich Schmid, E182 - 2; Alexander Kößler, E182 - 2

    A. Pavlogiannis, K. Chatterjee, U. Schmid, A. Kößler:
    "A Framework for Automated Competitive Analysis of On-line Scheduling of Firm-Deadline Tasks";
    Vortrag: 35th IEEE Real-Time Systems Symposium, Rome; 02.12.2014 - 05.12.2014; in: "Proccedings IEEE Real-Time Systems Symposium (RTSS'14)", (2014), ISSN: 1052-8725; S. 118 - 127.

  459. Autor/innen: Rasmus Pedersen; Martin Schoeberl, E182 - 1

    R. Pedersen, M. Schoeberl:
    "An Embedded Support Vector Machine";
    Vortrag: 4th Workshop on Intelligent Solutions in Embedded Systems - (WISES06), Vienna, Austria; 30.06.2006; in: "Fourth International Workshop on Intelligent Solutions in Embedded Systems, Proceedings", (2006), ISBN: 3-902463-06-6; S. 79 - 89.

    Zusätzliche Informationen

  460. Autor/innen: Rasmus Pedersen; Martin Schoeberl, E182 - 1

    R. Pedersen, M. Schoeberl:
    "Exact Roots for a Real-Time Garbage Collector";
    Vortrag: Workshop on Java Technologies for Real-time and Embedded Systems (JTRES), Paris, France; 11.10.2006 - 13.10.2006; in: "The 4th Workshop on Java Technologies for Real-time and Embedded Systems (JTRES 2006), Proceedings of", ACM Press (2006), ISBN: 1-59593-544-4; S. 77 - 84.

    Zusätzliche Informationen

  461. Autor/innen: Martin Perner, E182 - 2; Ulrich Schmid, E182 - 2; Christoph Lenzen; Martin Sigl, E182 - 2

    M. Perner, U. Schmid, C. Lenzen, M. Sigl:
    "Byzantine Self-Stabilizing Clock Distribution with HEX: Implementation, Simulation, Clock Multiplication";
    Vortrag: DEPEND 2013, The Sixth International Conference on Dependability, Barcelona, Spain; 25.08.2013 - 31.08.2013; in: "Proceedings of the 6th IARA International Conference on Dependability (DEPEND'13)", IARA, (2013), ISBN: 978-1-61208-301-8; S. 6 - 15.

    Zusätzliche Informationen

  462. Autor/innen: Philipp Peti, E182 - 1; Roman Obermaisser, Universität Siegen

    P. Peti, R. Obermaisser:
    "A Diagnostic Framework for Integrated Time-Triggered Architectures";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Gyeongju, Korea; 24.04.2006 - 26.04.2006; in: "9th IEEE International Symposium on Object and component-oriented Real-time distributed Computing, Proceedings of the", IEEE, (2006), ISBN: 0-7695-2561-x.

    Zusätzliche Informationen

  463. Autor/innen: Philipp Peti, E182 - 1; Roman Obermaisser, Universität Siegen; Astrit Ademaj, E182 - 1; Hermann Kopetz, E182 - 1

    P. Peti, R. Obermaisser, A. Ademaj, H. Kopetz:
    "A Maintenance-Oriented Fault Model for the DECOS Integrated Diagnostic Architecture";
    Vortrag: Workshop on Parallel and Distributed Real-Time Systems (WPDRTS), Denver, Colorado; 04.04.2005 - 08.04.2005; in: "Proceedings of the 13th Workshop on Parallel and Distributed Real-Time Systems 2005 (WPDRTS) Author(s)", (2005), ISBN: 0-7695-2312-9.

  464. Autor/innen: Philipp Peti, E182 - 1; Roman Obermaisser, Universität Siegen; Wilfried Elmenreich, E182 - 1; Thomas Losert, E182 - 1

    P. Peti, R. Obermaisser, W. Elmenreich, T. Losert:
    "An Architecture supporting Monitoring and Configuration in Real-Time Smart Transducer Networks";
    Vortrag: IEEE International Conference on Sensors, Orlando, Florida; 01.06.2002; in: "Proceedings of the First IEEE International Conference on Sensors ", 2 (2002), S. 1479 - 1484.

    Zusätzliche Informationen

  465. Autor/innen: Philipp Peti, E182 - 1; Roman Obermaisser, Universität Siegen; Hermann Kopetz, E182 - 1

    P. Peti, R. Obermaisser, H. Kopetz:
    "Out-of-Norm Assertions";
    Vortrag: IEEE Real-Time and Embedded Technology and Applications Symposium, San Francisco, California; 07.03.2005 - 10.03.2005; in: "Proceedings of the elventh IEEE Real-Time and Embedded Technology and Applications Symposium", IEEE Computer Society, (2005), ISBN: 0-7695-2302-1; S. 280 - 291.

    Zusätzliche Informationen

  466. Autor/innen: Philipp Peti, E182 - 1; Roman Obermaisser, Universität Siegen; Harald Paulitsch, E182 - 1

    P. Peti, R. Obermaisser, H. Paulitsch:
    "The Diagnostic Architecture of the PEGASUS Project Car";
    Vortrag: 3rd Workshop on Intelligent Solutions in Embedded Systems (WISES'05), Hamburg, Germany; 20.05.2005; in: "Proceedings of the 3rd Workshop on Intelligent Solutions in Embedded Systems (WISES'05)", IEEE Catalog Number 05EX1101 (2005), ISBN: 3-902463-03-1; S. 163 - 174.

    Zusätzliche Informationen

  467. Autor/innen: Philipp Peti, E182 - 1; Roman Obermaisser, Universität Siegen; Fulvio Tagliabo; Antonio Marino; Stefano Cerchio

    P. Peti, R. Obermaisser, F. Tagliabo, A. Marino, S. Cerchio:
    "An Integrated Architecture for Future Car Generations";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Seattle, Washington; 18.05.2005 - 20.05.2005; in: "Proceedings of the 8th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing", (2005), ISBN: 0-7695-2356-0; S. 2 - 13.

    Zusätzliche Informationen

  468. Autor/innen: Philipp Peti, E182 - 1; Harald Paulitsch, E182 - 1; Roman Obermaisser, Universität Siegen

    P. Peti, H. Paulitsch, R. Obermaisser:
    "Investigating Connector Faults in the Time-Triggered Architecture";
    Vortrag: ETFA, Prague, Czech Republic; 20.09.2006 - 22.09.2006; in: "11th IEEE International Conference on Emerging Technologies and Factory Automation , Proceedings", (2006).

    Zusätzliche Informationen

  469. Autor/innen: Daniel Pfleger; Ulrich Schmid, E182 - 2

    D. Pfleger, U. Schmid:
    "A Framework for Connectivity Monitoring in Wireless Sensor Networks";
    Vortrag: 10th International Conference on Sensor Technlogies and Applications (SENSORCOMM'16), Nice, France; 24.07.2016 - 28.07.2016; in: "Proceedings 10th International Conference on Sensor Technlogies and Applications (SENSORCOMM'16)", IARIA XPS Press, (2016), ISBN: 978-1-61208-490-9; S. 40 - 48.

    Zusätzliche Informationen

  470. Autor/innen: Dung Phan; Junxing Yang; Denise Ratasich, E182 - 1; Radu Grosu, E182 - 1; Scott A. Smolka, Stony Brook U; Scott D. Stoller, Stony Brook U

    D. Phan, J. Yang, D. Ratasich, R. Grosu, S. Smolka, S. Stoller:
    "Collision Avoidance for Mobile Robots with Limited Sensing in Unknown Environments";
    Vortrag: RV 2015, the 6th International Conference on Runtime Verification, Vienna; 22.09.2015 - 25.09.2015; in: "Runtime Verification, 6th International Conference (RV 2015)", Springer, 9333 (2015), ISBN: 978-3-319-23819-7; S. 201 - 215.

    Zusätzliche Informationen

  471. Autor/in: Christof Pitter, E182 - 1

    C. Pitter:
    "JopCMP - A Java Chip-Multiprocessor for Real-time Systems";
    Poster: 4th International Workshop on Reconfigurable Communication Centric System-on-Chips, Workshop Proceedings (ReCoSoC), Barcelona, Spain; 09.07.2008 - 11.07.2008; in: "4th International Workshop on Reconfigurable Communication Centric System-on-Chips, Workshop Proceedings", DFG, (2008), ISBN: 978-84-691-3603-4; Paper-Nr. p9, 3 S.

    Zusätzliche Informationen

  472. Autor/in: Christof Pitter, E182 - 1

    C. Pitter:
    "Time-predictable memory arbitration for a Java chip-multiprocessor";
    Vortrag: Workshop on Java Technologies for Real-time and Embedded Systems (JTRES), Santa Clara, California; 24.09.2008 - 26.09.2008; in: "Proceedings of the 6th international workshop on Java technologies for real-time and embedded systems", ACM, (2008), ISBN: 978-1-60558-337-2; S. 115 - 122.

    Zusätzliche Informationen

  473. Autor/innen: Christof Pitter, E182 - 1; Martin Schoeberl, E182 - 1

    C. Pitter, M. Schoeberl:
    "Performance Evaluation of a Java Chip-Multiprocessor";
    Vortrag: SIES´2008 Third international symposium on industrial embedded systems, Montpellier - La Grande Motte, France; 11.08.2008 - 13.08.2008; in: "SIES´2008 Third international symposium on industrial embedded systems", (2008), ISBN: 978-1-4244-1995-1; S. 34 - 42.

    Zusätzliche Informationen

  474. Autor/innen: Christof Pitter, E182 - 1; Martin Schoeberl, E182 - 1

    C. Pitter, M. Schoeberl:
    "Time Predictable CPU and DMA Shared Memory Access";
    Vortrag: 17th International Conference on Field Programmable Logic and Applications (FPL2007), Amsterdam, Netherlands; 27.08.2007 - 29.08.2007; in: "2007 International Conference on Field Programmable Logic and Applications (FPL)", IEEE, 07EX1708C (2007), ISBN: 1-4244-1060-6; S. 317 - 322.

    Zusätzliche Informationen

  475. Autor/innen: Christof Pitter, E182 - 1; Martin Schoeberl, E182 - 1

    C. Pitter, M. Schoeberl:
    "Towards a Java multiprocessor";
    Vortrag: Workshop on Java Technologies for Real-time and Embedded Systems (JTRES), Vienna, Austria; 26.09.2007 - 28.09.2007; in: "Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems", ACM, (2007), 978-59593-813-8; S. 144 - 151.

    Zusätzliche Informationen

  476. Autor/innen: Stefan Pitzek, E182 - 1; Wilfried Elmenreich, E182 - 1

    S. Pitzek, W. Elmenreich:
    "Configuration and Management of a Real-Time Smart Transducer Network";
    Vortrag: IEEE Conference on Emerging Technologies and Factory Automation, Lisbon, Portugal; 16.09.2003 - 19.09.2003; in: "Proceedings of the IEEE Conference on Emerging Technologies and Factory Automation", (2003), S. 407 - 414.

    Zusätzliche Informationen

  477. Autor/innen: Stefan Pitzek, E182 - 1; Wilfried Elmenreich, E182 - 1

    S. Pitzek, W. Elmenreich:
    "Managing Fieldbus Systems";
    Vortrag: Euromicro International Conference, Vienna, Austria; 19.06.2002 - 21.06.2002; in: "Proceedings of the Work-in-Progress Session of the 14th Euromicro International Conference", (2002), S. 13 - 16.

    Zusätzliche Informationen

  478. Autor/innen: Stefan Pitzek, E182 - 1; Wilfried Elmenreich, E182 - 1

    S. Pitzek, W. Elmenreich:
    "Plug-and-Play: Bridging the Semantic Gap Between Application and Transducers";
    Vortrag: ETFA, Catania, Italy; 19.09.2005 - 22.09.2005; in: "Proceedings of the 10th IEEE Internationla Conference on Emerging Technologies and Factory Automation", IEEE, I (2005), ISBN: 0-7803-9402-x; S. 799 - 806.

    Zusätzliche Informationen

  479. Autor/innen: Stefan Pitzek, E182 - 1; Peter Puschner, E182 - 1

    S. Pitzek, P. Puschner:
    " Function Test Environment for Embedded Driver Components";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Vienna, Austria; 12.05.2004 - 14.05.2004; in: "Proceedings of the IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2004)", IEEE, (2004), ISBN: 0-7695-2124-x; S. 237 - 244.

    Zusätzliche Informationen

  480. Autor/innen: Stefan Pitzek, E182 - 1; Peter Puschner, E182 - 1
    Andere beteiligte Person: Wilfried Elmenreich, E182 - 1

    S. Pitzek, P. Puschner:
    "Function Test Framework for Testing IO-Blocks in a Model-Based Rapid Prototyping Development Environment for Embedded Control Applications";
    Vortrag: Workshop on Intelligent Solutions in Embedded Systems, Vienna, Austria; 27.06.2003; in: "Proceedings of the First Workshop on Intelligent Solutions in Embedded Systems", W. Elmenreich (Hrg.); (2003), S. 85 - 96.

    Zusätzliche Informationen

  481. Autor/innen: Thomas Polzer, E182 - 2; Thomas Handl, E182 - 2; Andreas Steininger, E182 - 2

    T. Polzer, T. Handl, A. Steininger:
    "A Metastability-Free Multi-synchronous Communication Scheme for SoCs";
    Vortrag: SSS 2009 (Symposium on Stabilization, Safety, and Security of Distributed Systems), Lyon, France; 03.11.2009 - 06.11.2009; in: "Stabilization, Safety, and Security of Distribiuted Systems", Springer, 5873/2009 (2009), ISBN: 978-3642051173; S. 578 - 592.

    Zusätzliche Informationen

  482. Autor/innen: Thomas Polzer, E182 - 2; Florian Huemer, E182 - 2; Andreas Steininger, E182 - 2

    T. Polzer, F. Huemer, A. Steininger:
    "A Programmable Delay Line for Metastability Characterization in FPGAs";
    Vortrag: 24th Austrian Workshop on Microelectronics (Austrochip), Villach; 19.10.2016; in: "Proceedings 24th Austrian Workshop on Microelectronics", (2016), 6 S.

    Zusätzliche Informationen

  483. Autor/innen: Thomas Polzer, E182 - 2; Andreas Steininger, E182 - 2

    T. Polzer, A. Steininger:
    "A General Approach for Comparing Metastable Behavior of Digital CMOS Gates";
    Vortrag: 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Kosice, Slovakia; 20.04.2016 - 22.04.2016; in: "Proc 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", (2016), ISBN: 978-1-5090-2467-4; 6 S.

    Zusätzliche Informationen

  484. Autor/innen: Thomas Polzer, E182 - 2; Andreas Steininger, E182 - 2

    T. Polzer, A. Steininger:
    "An Approach for Efficient Metastability Characterization of FPGAs through the Designer";
    Vortrag: 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2013), Santa Monica, CA; 19.05.2013 - 22.05.2013; in: "19th IEEE International Symposium on Asynchronous Circuits and Systems", (2013), ISSN: 1522-8681; 9 S.

    Zusätzliche Informationen

  485. Autor/innen: Thomas Polzer, E182 - 2; Andreas Steininger, E182 - 2

    T. Polzer, A. Steininger:
    "Digital Late-Transition Metastability Simulation Model";
    Vortrag: 16th Euromicro Conference on Digital System Design (DSD 2013), Santander; 04.09.2013 - 06.09.2013; in: "Proceedings of the 16th Euromicro Conference on Digital System Design", (2013), 8 S.

    Zusätzliche Informationen

  486. Autor/innen: Thomas Polzer, E182 - 2; Andreas Steininger, E182 - 2

    T. Polzer, A. Steininger:
    "Enhanced Metastability Characterization based on AC Analysis";
    Vortrag: 18th Euromicro Conference on Digital System Design, Funchal, Portugal; 26.08.2015 - 28.08.2015; in: "18th Euromicro Conference on Digital System Design", (2015), 9 S.

    Zusätzliche Informationen

  487. Autor/innen: Thomas Polzer, E182 - 2; Andreas Steininger, E182 - 2

    T. Polzer, A. Steininger:
    "Measuring the Distribution of Metastable Upsets over Time";
    Vortrag: 18th Euromicro Conference on Digital System Design, Funchal, Portugal; 26.08.2015 - 28.08.2015; in: "Measuring the Distribution of Metastable Upsets over Time", (2015), 8 S.

    Zusätzliche Informationen

  488. Autor/innen: Thomas Polzer, E182 - 2; Andreas Steininger, E182 - 2

    T. Polzer, A. Steininger:
    "Metastability Characterization for Muller C-Elements";
    Vortrag: 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013), Karlsruhe; 09.09.2013 - 11.09.2013; in: "23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013)", (2013), 8 S.

    Zusätzliche Informationen

  489. Autor/innen: Thomas Polzer, E182 - 2; Andreas Steininger, E182 - 2

    T. Polzer, A. Steininger:
    "SET Propagation in Micropipelines";
    Vortrag: 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013), Karlsruhe; 09.09.2013 - 11.09.2013; in: "23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013)", (2013), 8 S.

    Zusätzliche Informationen

  490. Autor/innen: Thomas Polzer, E182 - 2; Andreas Steininger, E182 - 2; Jakob Lechner, E182 - 2

    T. Polzer, A. Steininger, J. Lechner:
    "Muller C-Element Metastability Containment";
    Vortrag: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2012, Newcastle upon Tyne; 04.09.2012 - 06.09.2012; in: "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation", Lecture Notes in Computer Science, 7606 (2013), ISBN: 978-3-642-36156-2; S. 103 - 112.

    Zusätzliche Informationen

  491. Autor/innen: Adrian Prantl, E185 - 1; Jens Knoop, E185 - 1; Raimund Kirner, E182 - 1; Albrecht Kadlec, E182 - 1; Markus Schordan
    Andere beteiligte Personen: Jens Knoop, E185 - 1; Adrian Prantl, E185 - 1

    A. Prantl, J. Knoop, R. Kirner, A. Kadlec, M Schordan:
    "From Trusted Annotations to Verified Knowledge";
    Vortrag: 15. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS 2009), Maria Taferl; 12.10.2009 - 14.10.2009; in: "15. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS 2009)", J. Knoop, A. Prantl (Hrg.); Schriftenreihe des Instituts für Computersprachen, TU Wien, Bericht 2009-X-1 (2009), S. 155 - 166.

    Zusätzliche Informationen

  492. Autor/innen: Adrian Prantl, E185 - 1; Jens Knoop, E185 - 1; Raimund Kirner, E182 - 1; Markus Schordan; Albrecht Kadlec, E182 - 1
    Andere beteiligte Person: Niklas Holsti

    A. Prantl, J. Knoop, R. Kirner, M Schordan, A. Kadlec:
    "From Trusted Annotations to Verified Knowledge";
    Vortrag: 9th International Workshop on Worst-Case Execution Time Analysis (WCET 2009), Dublin, Ireland; 30.06.2009; in: "Preliminary Proceedings of the 9th International Workshop on Worst-Case Execution Time Analysis (WCET 2009)", N. Holsti (Hrg.); (2009), S. 35 - 45.

  493. Autor/innen: Daniel Prokesch, E182 - 1; Stefan Hepp, E185 - 1; Peter Puschner, E182 - 1

    D. Prokesch, S Hepp, P. Puschner:
    "A Generator for Time-Predictable Code";
    Vortrag: 18th IEEE International Symposium on Real-Time Computing (ISORC 2015), Auckland, New Zealand; 13.04.2015 - 17.04.2015; in: "Proc. 18th IEEE International Symposium on Real-Time Computing (ISORC 2015)", IEEE, (2015), ISBN: 978-1-4799-8781-8; S. 27 - 34.

    Zusätzliche Informationen

  494. Autor/innen: Daniel Prokesch, E182 - 1; Benedikt Huber, E182 - 1; Peter Puschner, E182 - 1

    D. Prokesch, B. Huber, P. Puschner:
    "Towards Automated Generation of Time-Predictable Code";
    Vortrag: 14th International Workshop on Worst-Case Execution Time Analysis (WCET 2014), Madrid; 08.07.2014; in: "14th International Workshop on Worst-Case Execution Time Analysis", Dagstuhl, Germany (2014), ISBN: 978-3-939897-69-9; S. 103 - 112.

    Zusätzliche Informationen

  495. Autor/innen: Daniel Prokesch, E182 - 1; Peter Puschner, E182 - 1

    D. Prokesch, P. Puschner:
    "A Strategy for Generating Time-Predictable Code";
    Vortrag: 18. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS) 2015, Pörtschach am Wörthersee; 04.10.2015 - 07.10.2015; in: "18. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS) 2015", (2015).

    Zusätzliche Informationen

  496. Autor/innen: Markus Proske, E182 - 2; Christian Trödhandl, E182 - 1

    M. Proske, C. Trödhandl:
    "Anytime, Everywhere - Approaches to Distance Labs in Embedded Systems Education";
    Vortrag: ICTTA06: International Conference on Information & Communication Technologies, Damascus; 24.04.2006 - 28.04.2006; in: "Proceedings of ICTTA 2006", (2006), 6 S.

    Zusätzliche Informationen

  497. Autor/innen: Markus Proske, E182 - 2; Christian Trödhandl, E182 - 1; Thomas Handl, E182 - 2

    M. Proske, C. Trödhandl, T. Handl:
    "Distance Labs - Embedded Systems @home";
    Vortrag: Edutainment 2006, Zhejiang; 14.04.2006 - 18.04.2006; in: "Journal of Computational Information Systems", (2006), S. 435 - 444.

    Zusätzliche Informationen

  498. Autor/in: Wolfgang Puffitsch, E182 - 1

    W. Puffitsch:
    "Data Caching, Garbage Collection, and the Java Memory Model";
    Vortrag: Proceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems (JTRES09), Madrid, Spain; 23.09.2009 - 25.09.2009; in: "Proceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems", ACM Digital Library, (2009), ISBN: 978-1-60558-732-5; S. 130 - 139.

    Zusätzliche Informationen

  499. Autor/in: Wolfgang Puffitsch, E182 - 1

    W. Puffitsch:
    "Decoupled Root Scanning in Multi-Processor Systems";
    Poster: Embedded Systems Week 2008 (ESWEEK08), Atlanta, Georgia, USA; 19.10.2008 - 24.10.2008; in: "Embedded Systems Week", ACM, (2008), ISBN: 978-1-60558-471-3; 8 S.

    Zusätzliche Informationen

  500. Autor/in: Wolfgang Puffitsch, E182 - 1

    W. Puffitsch:
    "Hard Real-Time Garbage Collection for a Java Chip Multi-Processor";
    Vortrag: 9th International Workshop on Java Technologies for Real-Time and Embedded Systems (JTRES 2011), York, United Kingdom; 26.09.2011 - 28.09.2011; in: "Proceedings of the 9th International Workshop on Java Technologies for Real-Time and Embedded Systems", ACM, (2011).

    Zusätzliche Informationen

  501. Autor/innen: Wolfgang Puffitsch, E182 - 1; Benedikt Huber, E182 - 1; Martin Schoeberl, E182 - 1

    W. Puffitsch, B. Huber, M. Schoeberl:
    "Worst-Case Analysis of Heap Allocations";
    Vortrag: 4th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation (ISoLA 2010), Heraklion, Griechenland; 18.10.2010 - 20.10.2010; in: "Worst-Case Analysis of Heap Allocations", Lecture Notes in Computer Science, 6416 (2010), S. 464 - 478.

    Zusätzliche Informationen

  502. Autor/innen: Wolfgang Puffitsch, E182 - 1; Martin Schoeberl, E182 - 1

    W. Puffitsch, M. Schoeberl:
    "picoJava-II in an FPGA";
    Vortrag: Workshop on Java Technologies for Real-time and Embedded Systems (JTRES), Vienna, Austria; 26.09.2007 - 28.09.2007; in: "Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems", ACM, (2007), 978-59593-813-8; S. 213 - 221.

    Zusätzliche Informationen

  503. Autor/in: Peter Puschner, E182 - 1

    P. Puschner:
    "Algorithms for Dependable Hard Real-Time Systems";
    Vortrag: IEEE International Workshop on Object-Oriented Real-Time Dependable Systems, Guadalajara, Mexico; 15.01.2003 - 17.01.2003; in: "Proceedings of the 8th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems", (2003), S. 26 - 31.

    Zusätzliche Informationen

  504. Autor/in: Peter Puschner, E182 - 1

    P. Puschner:
    "Architecture Support for Temporal Predictability and Composability in Real-Time Computing";
    Hauptvortrag: 4th International Conference on Information and 4th Irish Conference on the Mathematical Foundations of Computer Science and Information Technology, Cork, Ireland (eingeladen); 01.08.2006 - 05.08.2006; in: "4th International Conference on Information and 4th Irish Conference on the Mathematical Foundations of Computer Science and Information Technology, Proceedings", (2006), S. #1.

    Zusätzliche Informationen

  505. Autor/in: Peter Puschner, E182 - 1

    P. Puschner:
    "Constructing Time-Critical Embedded Systems: Decide Before Runtime";
    Hauptvortrag: Second Mediterranean Conference on Embedded Computing, Budva, Montenegro (eingeladen); 15.06.2013 - 20.06.2013; in: "Proceedings 2nd Mediterranean Conference on Embedded Computing (MECO)", IEEE, (2013), ISBN: 978-9940-9436-1-5; S. 3.

    Zusätzliche Informationen

  506. Autor/in: Peter Puschner, E182 - 1

    P. Puschner:
    "Embedded Systems for Safety-Critical and Mixed-Criticality Applications";
    Hauptvortrag: Second Mediterranean Conference on Embedded Computing, Budva, Montenegro (eingeladen); 15.06.2013 - 20.06.2013; in: "Proceedings 2nd Mediterranean Conference on Embedded Computing (MECO)", IEEE, (2013), ISBN: 978-9940-9436-1-5; S. 15.

    Zusätzliche Informationen

  507. Autor/in: Peter Puschner, E182 - 1

    P. Puschner:
    "Experiments with WCET-Oriented Programming and the Single-Path Architecture RR Number";
    Vortrag: IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS), Sedona, Arizona; 02.02.2005 - 04.02.2005; in: "Proceedings of the 10th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems, 2005", (2005), ISBN: 0-7695-2347-1; S. 205 - 210.

    Zusätzliche Informationen

  508. Autor/in: Peter Puschner, E182 - 1

    P. Puschner:
    "Hard Real-Time Programming is Different";
    Vortrag: 17th International Parallel and Distributed Processing Symposium, Nice, France; 22.04.2003 - 26.04.2003; in: "Proceedings of the 17th IEEE Int'l Parallel and Distributed Processing Symposium, 11th Int'l workshop on Parallel and Distributed Real-Time Systems 2003", (2003), S. 117 - 118.

    Zusätzliche Informationen

  509. Autor/in: Peter Puschner, E182 - 1

    P. Puschner:
    "Is Worst-Case Execution-Time Analysis a Non-Problem? -- Towards New Software and Hardware Architectures";
    Vortrag: Euromicro International Workshop on WCET Analysis, Vienna, Austria; 18.06.2002; in: "Proceedings of the 2nd Euromicro International Workshop on WCET Analysis", (2002).

    Zusätzliche Informationen

  510. Autor/in: Peter Puschner, E182 - 1

    P. Puschner:
    "Making Real-Time Tasks Temporally Predictable";
    Vortrag: ARTES Real-Time Graduate Student Conference, Uppsala, Sweden; 18.04.2002 - 19.04.2002; in: "Proceedings of the ARTES Real-Time Graduate Student Conference ", (2002), S. 7.

    Zusätzliche Informationen

  511. Autor/in: Peter Puschner, E182 - 1

    P. Puschner:
    "The Single-Path Approach Towards WCET-Analysable Software";
    Vortrag: IEEE International Conference on Industrial Technology, Maribor, Slovenia; 10.12.2003 - 12.12.2003; in: "Proceedings of IEEE International Conference on Industrial Technology", (2003), S. 699 - 704.

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  512. Autor/innen: Peter Puschner, E182 - 1; Guillem Bernat

    P. Puschner, G. Bernat:
    "WCET Analysis of Reusable Portable Code";
    Vortrag: Euromicro Conference on Real-Time Systems (ECRTS), Delft, Netherlands; 01.11.2001; in: "Proceedings of the Euromicro Conference on Real-Time Systems (ECRTS)", (2001), S. 45 - 52.

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  513. Autor/innen: Peter Puschner, E182 - 1; Alan Burns

    P. Puschner, A. Burns:
    "Writing Temporally Predictable Code";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), San Diego, USA; 07.01.2002 - 09.01.2002; in: "Proceedings of the 7th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems", (2002), S. 85 - 91.

    Zusätzliche Informationen

  514. Autor/innen: Peter Puschner, E182 - 1; Bekim Cilku, E182 - 1; Daniel Prokesch, E182 - 1

    P. Puschner, B. Cilku, D. Prokesch:
    "Constructing Time-Predictable MPSoCs: Avoid Conflicts in Temporal Control";
    Vortrag: IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Lyon, Frankreich; 21.09.2016 - 23.09.2016; in: "Proceedings IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip", 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems on Chip; ISBN 978-1-5090-3530-4, (2016), ISBN: 978-1-5090-3530-4; S. 321 - 328.

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  515. Autor/innen: Peter Puschner, E182 - 1; Bernhard Frömel, E182 - 1

    P. Puschner, B. Frömel:
    "Composable Component Interfaces for Time-Triggered Systems";
    Vortrag: 12th International IEEE/IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2016), York, UK; 19.05.2016; in: "Proc. 19th IEEE International Symposium on Real-Time Computing (ISORC 2016) Workshops", (2016).

    Zusätzliche Informationen

  516. Autor/innen: Peter Puschner, E182 - 1; Raimund Kirner, E182 - 1

    P. Puschner, R. Kirner:
    "Avoiding Timing Problems in Real-Time Software";
    Vortrag: IEEE Workshop on Software Technologies for Future Embedded Systems, Hakodate, Hokkaido, Japan; 15.05.2003 - 16.05.2003; in: "Proceedings of the IEEE Workshop on Software Technologies for Future Embedded Systems, 2003", (2003), S. 75 - 78.

    Zusätzliche Informationen

  517. Autor/innen: Peter Puschner, E182 - 1; Raimund Kirner, E182 - 1

    P. Puschner, R. Kirner:
    "From Time-Triggered to Time-Deterministic Real-Time Systems";
    Vortrag: IFIP Working Conference on Distributed and Parallel Embedded Systems, Braga, Portugal (eingeladen); 11.10.2006 - 13.10.2006; in: "5th IFIP Working Conference on Distributed and Parallel Embedded Systems, Proceedings", Springer, (2006), ISBN: 0-387-39361-7; S. 115 - 124.

    Zusätzliche Informationen

  518. Autor/innen: Peter Puschner, E182 - 1; Raimund Kirner, E182 - 1

    P. Puschner, R. Kirner:
    "Model-Driven Design and Organic Computing -- Combinable Strategies?";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Tokyo, Japan; 17.03.2009 - 20.03.2009; in: "12th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing", IEEE, (2009), S. 101.

  519. Autor/innen: Peter Puschner, E182 - 1; Raimund Kirner, E182 - 1; Robert G. Pettit

    P. Puschner, R. Kirner, R. Pettit:
    "Towards Composable Timing for Real-Time Software";
    Vortrag: First International Workshop on Software Technologies for Future Dependable Distributed Systems (STFSSD 2009), Tokyo, Japan; 17.03.2009 - 18.03.2009; in: "2009 Software Technologies for Future Dependable Distributed Systems", IEEE, (2009), ISBN: 978-0-7695-3572-2; S. 1 - 5.

    Zusätzliche Informationen

  520. Autor/innen: Peter Puschner, E182 - 1; Raimund Kirner; Daniel Prokesch, E182 - 1; Benedikt Huber, E182 - 1

    P. Puschner, R. Kirner, D. Prokesch, B. Huber:
    "Compiling for Time Predictability";
    Vortrag: ERCIM/EWICS/Cyberphysical Systems Workshop, Magdeburg, Germany; 25.09.2012 - 28.09.2012; in: "Computer Safety, Reliability, and Security - SAFECOMP 2012 Workshops", Lecture Notes in Computer Science / Springer, 7613 (2012), ISBN: 978-3-642-33674-4; S. 382 - 391.

    Zusätzliche Informationen

  521. Autor/innen: Peter Puschner, E182 - 1; Daniel Prokesch, E182 - 1; Benedikt Huber, E182 - 1; Jens Knoop, E185 - 1; Stefan Hepp, E185 - 1; Gernot Gebhard

    P. Puschner, D. Prokesch, B. Huber, J. Knoop, S Hepp, G. Gebhard:
    "The T-CREST Approach of Compiler and WCET-Analysis Integration";
    Vortrag: 9th Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2013), Paderborn, Deutschland (eingeladen); 17.06.2013 - 18.06.2013; in: "Proceedings of the 9th Workshop on Software Technologies for Future Embedded and Ubiquitous Systems", (2013).

  522. Autor/innen: Peter Puschner, E182 - 1; Martin Schoeberl, E182 - 1

    P. Puschner, M. Schoeberl:
    "On Composable System Timing, Task Timing, and WCET Analysis";
    Vortrag: WCET 2008, Prague, Czech Republic; 01.07.2008; in: "Worst-Case Execution Time Analysis; Proceedings of the 8th International Workshop (WCET 2008)", Österreichische Computer Gesellschaft, (2008), ISBN: 978-3-85403-237-3; S. 91 - 101.

    Zusätzliche Informationen

  523. Autor/innen: Peter Puschner, E182 - 1; Andy Wellings

    P. Puschner, A. Wellings:
    "A Profile for High-Integrity Real-Time Java Programs";
    Vortrag: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Magdeburg, Germany; 02.05.2001 - 04.05.2001; in: "Proceedings of the 4th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC)", (2001), S. 15 - 22.

    Zusätzliche Informationen

  524. Autor/innen: Babak Rahbaran, E182 - 2; Matthias Függer, E182 - 2; Andreas Steininger, E182 - 2

    B. Rahbaran, M Függer, A. Steininger:
    "Embedded Real-Time-Tracer --An Approach with IDE";
    Vortrag: Workshop on Intelligent Solutions in Embedded Systems, Austria, Graz; 25.06.2004; in: "Proceedings of the Second Workshop on Intelligent Solutions in Embedded Systems", (2004), ISBN: 3-902463-00-7; S. 25 - 35.

    Zusätzliche Informationen

  525. Autor/innen: Babak Rahbaran, E182 - 2; Andreas Steininger, E182 - 2

    B. Rahbaran, A. Steininger:
    "Real-time Fault Injection with Signal-Flip model by FIDYCO";
    Vortrag: IEEE International Conference on Dependable Systems and Networks, Florence, Italy; 28.06.2004 - 01.07.2004; in: "DSN 2004 Supplement", IEEE Computer Society, Supplemental (2004), S. 70 - 71.

  526. Autor/innen: Babak Rahbaran, E182 - 2; Andreas Steininger, E182 - 2; Thomas Handl, E182 - 2
    Andere beteiligte Personen: Babak Rahbaran, E182 - 2; Andreas Steininger, E182 - 2

    B. Rahbaran, A. Steininger, T. Handl:
    "Built-in Fault Injection in Hardware-- The FIDYCO Example";
    Vortrag: IEEE International Workshop on Electronic Design, Test and Applications, Perth, Australia; 28.01.2004 - 30.01.2004; in: "Second IEEE International Workshop on Electronic Design, Test and Applications", B. Rahbaran, A. Steininger (Hrg.); IEEE Computer Society Press, Delta 2004, Perth Australia (2004), ISBN: 0-7695-2081-2; S. 327 - 332.

    Zusätzliche Informationen

  527. Autor/innen: Ray Rajarshi; Gurung Amit; Das Binayak; Ezio Bartocci, E182 - 1; Sergiy Bogomolov, Univ. Freiburg; Radu Grosu, E182 - 1

    R. Rajarshi, G. Amit, D. Binayak, E. Bartocci, S. Bogomolov, R. Grosu:
    "XSpeed: Accelerating Reachability Analysis on MultiCore Processors";
    Hauptvortrag: the 11th Haifa Verification Conference (HVC), Haifa, Israel; 17.11.2015 - 19.11.2015; in: "Proc. of HVC 2015: the 11th Haifa Verification Conference, Haifa, Israel, November, 2015", LNCS / Springer, 9434 (2015), ISBN: 978-3-319-26286-4; S. 3 - 18.

    Zusätzliche Informationen

  528. Autor/innen: Denise Ratasich, E182 - 1; Bernhard Frömel, E182 - 1; Oliver Höftberger, E182 - 1; Radu Grosu, E182 - 1

    D. Ratasich, B. Frömel, O. Höftberger, R. Grosu:
    "Generic Sensor Fusion Package for ROS";
    Vortrag: 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), Hamburg; 28.09.2015 - 02.10.2015; in: "Intelligent Robots and Systems (IROS), 2015 IEEE/RSJ International Conference on", IEEE, (2015), S. 286 - 291.

    Zusätzliche Informationen

  529. Autor/innen: Semeen Rehman, TUD; Walaa El-Harouni, KIT; Muhammad Shafique, E182 - 2; Akash Kumar, TUD; Jörg Henkel, KIT

    S. Rehman, W. El-Harouni, M. Shafique, A. Kumar, J. Henkel:
    "Architectural-Space Exploration of Approximate Multipliers";
    Vortrag: The IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, USA; 07.11.2016 - 10.11.2016; in: "ICCAD", ACM New York, NY, USA, (2016), ISBN: 978-1-4503-4466-1.

    Zusätzliche Informationen

  530. Autor/innen: Thomas Reinbacher, E182; Jörg Brauer

    T. Reinbacher, J. Brauer:
    "Precise control flow reconstruction using boolean logic";
    Vortrag: EMSOFT2011, ACM international conference on Embedded software, Taipei; 09.10.2011 - 14.10.2011; in: "EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software", ACM New York, (2011), ISBN: 978-1-4503-0714-7; S. 117 - 126.

    Zusätzliche Informationen

  531. Autor/innen: Thomas Reinbacher, E182; Jörg Brauer; Martin Horauer; Andreas Steininger, E182 - 2; Stefan Kowalewski

    T. Reinbacher, J. Brauer, M. Horauer, A. Steininger, S. Kowalewski:
    "Past time LTL runtime verification for microcontroller binary code";
    Vortrag: FMICS 2011, Trento; 29.08.2011 - 30.08.2011; in: "Formal Methods for Industrial Critical Systems", Springer Berlin / Heidelberg, (2011), ISBN: 978-3-642-24430-8; S. 37 - 51.

    Zusätzliche Informationen

  532. Autor/innen: Thomas Reinbacher, E182; Jörg Brauer; Martin Horauer; Andreas Steininger, E182 - 2; Stefan Kowalewski

    T. Reinbacher, J. Brauer, M. Horauer, A. Steininger, S. Kowalewski:
    "Test-Case Generation for Embedded Binary Code Using Abstract Interpretation";
    Vortrag: MEMICS 2010 (Mathematical and Engineering Methods in Computer Science), Mikulov, Czech Republic; 22.10.2010 - 24.10.2010; in: "MEMICS proceedings", (2010), S. 151 - 158.

    Zusätzliche Informationen

  533. Autor/innen: Thomas Reinbacher, E182; Jörg Brauer; Daniel Schachinger; Andreas Steininger, E182 - 2; Stefan Kowalewski

    T. Reinbacher, J. Brauer, D. Schachinger, A. Steininger, S. Kowalewski:
    "Automated test-trace inspection for microcontroller binary code";
    Vortrag: 2nd International Conference on Runtime Verification (RV 2011), San Francisco; 27.09.2011 - 30.09.2011; in: "Runtime Verification", (2011), S. 239 - 244.

    Zusätzliche Informationen

  534. Autor/innen: Thomas Reinbacher, E182; Matthias Függer, E182 - 2; Jörg Brauer

    T. Reinbacher, M Függer, J. Brauer:
    "Real-Time Runtime Verification on Chip";
    Vortrag: RV 2012: the 3rd International Conference on Runtime Verification, Istanbul; 25.09.2012 - 28.09.2012; in: "Proc. of RV 2012: the 3rd International Conference on Runtime Verification", LNCS / Springer, 7687 (2012).

    Zusätzliche Informationen

  535. Autor/innen: Thomas Reinbacher, E182; Johannes Geist; Patrick Moosbrugger; Martin Horauer; Andreas Steininger, E182 - 2

    T. Reinbacher, J. Geist, P. Moosbrugger, M. Horauer, A. Steininger:
    "Parallel Runtime Verification of Temporal Properties for Embedded Software";
    Vortrag: Mechatronics and Embedded Systems and Applications (MESA), 2012 IEEE/ASME International Conference on, Suzhou, China; 08.07.2012 - 10.07.2012; in: "Mechatronics and Embedded Systems and Applications (MESA), 2012 IEEE/ASME International Conference on", (2012), ISBN: 978-1-4673-2347-5; S. 224 - 231.

    Zusätzliche Informationen

  536. Autor/innen: Thomas Reinbacher, E182; Dominik Gückel; Martin Horauer

    T. Reinbacher, D. Gückel, M. Horauer:
    "Testing microcontroller software simulators";
    Vortrag: WS4C 2011, Berlin; 04.10.2011 - 07.10.2011; in: "Workshop on Software Language Engineering for Cyber-physical Systems", (2011).

    Zusätzliche Informationen

  537. Autor/innen: Thomas Reinbacher, E182; Martin Horauer; Andreas Steininger, E182 - 2

    T. Reinbacher, M. Horauer, A. Steininger:
    "A Runtime Verification Unit for Microcontrollers";
    Vortrag: System, Software, SoC and Silicon Debug Conference (S4D), 2012, Vienna, Austria; 19.09.2012 - 20.09.2012; in: "System, Software, SoC and Silicon Debug Conference (S4D), 2012", (2012), ISSN: 2114-3684; S. 1 - 6.

    Zusätzliche Informationen

  538. Autor/innen: Thomas Reinbacher, E182; Andreas Steininger, E182 - 2; Tobias Müller; Martin Horauer; Jörg Brauer; Stefan Kowalewski

    T. Reinbacher, A. Steininger, T. Müller, M. Horauer, J. Brauer, S. Kowalewski:
    "Hardware support for efficient testing of embedded software";
    Vortrag: The 7th ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications, Washington; 29.08.2011 - 31.08.2011; in: "International Conference on Mechatronic and Embedded Systems and Applications", ASME, (2011).

    Zusätzliche Informationen

  539. Autor/innen: Stefan Resch, Thales; Andreas Steininger, E182 - 2; Christoph Scherrer, Thales

    S. Resch, A. Steininger, C. Scherrer:
    "Software Composability and Mixed Criticality for Triple Modular Redundant Architectures";
    Vortrag: SASSUR Workshop 2013, Toulouse; 24.09.2013; in: "Proceedings of the 2013 SASSUR Workshop", (2013), 4 S.

    Zusätzliche Informationen

  540. Autor/innen: Bernhard Rieder, E182 - 1; Peter Puschner, E182 - 1

    B. Rieder, P. Puschner:
    "Hybrid Timing Analysis for ANSI-C Applications with Loops and Function Calls";
    Poster: Junior Scientist Conference 2008, Wien; 16.11.2008 - 18.11.2008; in: "Proceedings of the Junior Scientist Conference 2008", (2008), ISBN: 978-3-200-01612-5; S. 101 - 102.

  541. Autor/innen: Bernhard Rieder, E182 - 1; Peter Puschner, E182 - 1; Ingomar Wenzel, E182 - 1

    B. Rieder, P. Puschner, I. Wenzel:
    "Using Model Checking to Derive Loop Bounds of General Loops within ANSI-C Applications for Measurement Based WCET Analysis";
    Vortrag: Workshop on Intelligent Solutions in Embedded Systems (WISES'08), Regensburg, Germany; 10.07.2008 - 11.07.2008; in: "Proceedings of the Sixth Workshop on Intelligent Solutions in Embedded Systems", IEEE Computer Society, (2008), ISBN: 978-3-00-024989-1; S. 3 - 9.

    Zusätzliche Informationen

  542. Autor/innen: Bernhard Rieder, E182 - 1; Ingomar Wenzel, E182 - 1; Klaus Steinhammer, E182 - 1; Peter Puschner, E182 - 1

    B. Rieder, I. Wenzel, K. Steinhammer, P. Puschner:
    "Using a Runtime Measurement Device with Measurement-Based WCET Analysis";
    Poster: International Embedded Systems Symposiom (IESS'07), Irvine, Orange County, in Southern California (USA); 30.05.2007 - 01.06.2007; in: "Embedded System Design: Topics, Techniques and Trends", Springer Boston, Volume 231/2007 (2007), ISBN: 978-0-387-72257-3; S. 15 - 26.

    Zusätzliche Informationen

  543. Autor/innen: Peter Robinson, E182 - 2; Martin Biely, E182 - 2; Ulrich Schmid, E182 - 2

    P. Robinson, M. Biely, U. Schmid:
    "Brief Announcment: Weak Synchrony Models and Failure Detectors for Message Passing (k-)Set Agreement*";
    Vortrag: DISC 2009 (International Symposium on Distributed Computing), Elche, Spain; 23.09.2009 - 25.09.2009; in: "Distribiuted Computing", Springer, 5805/2009 (2009), ISBN: 978-3-642-04354-3; S. 360 - 361.

    Zusätzliche Informationen

  544. Autor/innen: Peter Robinson, E182 - 2; Ulrich Schmid, E182 - 2

    P. Robinson, U. Schmid:
    "The Asynchronous Bounded Cycle Model";
    Vortrag: 10 International Symposium on Stabilization, Safety, and Security of Distributed Systems (SSS 2008), Detroit, USA; 21.11.2008 - 23.11.2008; in: "Stabilization, Safety, and Security of Distributed Systems", Lecture Notes in Conputer Science / Springer Verlag, 5340 (2008), ISSN: 0302-9743; S. 246 - 262.

    Zusätzliche Informationen

  545. Autor/innen: Alena Rodionova, E182 - 1; Ezio Bartocci, E182 - 1; Dejan Nickovic, AIT; Radu Grosu, E182 - 1

    A. Rodionova, E. Bartocci, D. Nickovic, R. Grosu:
    "Temporal Logic as Filtering";
    Vortrag: Proceeding HSCC '16 - the 19th International Conference on Hybrid Systems: Computation and Control, Vienna; 12.04.2016 - 14.04.2016; in: "Proceeding HSCC '16 - Proceedings of the 19th International Conference on Hybrid Systems: Computation and Control", ACM, (2016), ISBN: 978-1-4503-3955-1; S. 11 - 20.

    Zusätzliche Informationen

  546. Autor/in: Bernhard Rumpler, E182 - 1

    B. Rumpler:
    "Complexity Management for Composable Real-Time Systems";
    Poster: IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Gyeongju, Korea; 24.04.2006 - 26.04.2006; in: "Proceedings of the 9th IEEE International Symposium on Object and component-oriented Real-time distributed Computing (ISORC06)", IEEE, (2006), S. 365 - 373.

    Zusätzliche Informationen

  547. Autor/innen: Bernhard Rumpler, E182 - 1; Wilfried Elmenreich, E182 - 1

    B. Rumpler, W. Elmenreich:
    "Considerations on the Complexity of Embedded Real-Time System Design Tasks";
    Vortrag: IEEE International Conference on Computational Cybernetics 2006 (ICCC'06), Talinn, Estonia; 20.08.2006 - 22.08.2006; in: "IEEE International Conference on Computational Cybernetics 2006 (ICCC'06), Proceedings of the", (2006), S. 55 - 60.

    Zusätzliche Informationen

  548. Autor/innen: Bernhard Rumpler, E182 - 1; Hermann Kopetz, E182 - 1

    B. Rumpler, H. Kopetz:
    "Design Comprehension of Time-Triggered Real-Time Systems";
    Vortrag: Junior Scientist Conference, Vienna, Austria; 19.04.2006 - 21.04.2006; in: "Proceedings of the Junior Scientist Conference 2006 (JSC'06)", (2006), S. 63 - 64.

    Zusätzliche Informationen

  549. Autor/innen: Christian Scheidler; Peter Puschner, E182 - 1; Samuel Boutin; Emmerich Fuchs, E182 - 1;