Vorträge und Posterpräsentationen (mit Tagungsband-Eintrag):
B. Goll, H. Zimmermann:
"A Low-Power 2-GSample/s Comparator in 120 nm CMOS Technology";
Vortrag: European Solid-State Circuits Conference,
Grenoble, France;
12.09.2005
- 16.09.2005; in: "Proceedings of ESSCIRC 2005",
(2005),
ISBN: 0-7803-9205-1;
S. 507
- 510.
Kurzfassung englisch:
This paper presents a comparator in 120nm digital CMOS technology with a supply voltage of 1.5V. In contrast to common comparator structures a delayed reset signal is used to enhance the output voltage difference with the help of charge injection. Furthermore the body effect of p-MOS transistors with their separated n-wells are used to lower their threshold voltage to have an increase in resolution. For characterization several BER (Bit-Error-Rate) measurements on the comparator have been made. For a BER of 10-9 the comparator is able to detect an input voltage difference of 9.5mV at a clock frequency of 1.5GHz and 16mV at 2.0GHz. The maximum power consumption of the comparator with two following additional transfer stages is 360μW at 2.0GHz.
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Erstellt aus der Publikationsdatenbank der Technischen Universität Wien.