[Back]

P. Belanovic, B. Knerr, M. Holzer, M. Rupp:
"A Fully Automated Environment for Verification of Virtual Prototypes";
EURASIP Journal on Applied Signal Processing, 2006 (2006), 1 - 12.

The extremely dynamic and competitive nature of the wireless communication systems market demands ever shorter times to market for new products. Virtual prototyping has emerged as one of the most promising techniques to offer the required time savings and resulting increases in design efficiency. A fully automated environment for development of virtual prototypes is presented here, offering maximal efficiency gains, and supporting both design and verification flows, from the algorithmic model to the virtual prototype. The environment employs automated verification pattern refinement to achieve increased reuse in the design process, as well as increased quality by reducing human coding errors.

http://aleph.ub.tuwien.ac.at/F?base=tuw01&func=find-c&ccl_term=AC06586042

http://publik.tuwien.ac.at/files/pub-et_11034.pdf