Vorträge und Posterpräsentationen (mit Tagungsband-Eintrag):
M. Holzer, B. Knerr, M. Rupp:
"Structural Verification in Minimal Time";
Vortrag: International Symposium on System-on-Chip (SOC),
Tampere, Finnland;
14.11.2006
- 16.11.2006; in: "International Symposium on System-on-Chip",
(2006),
ISBN: 1-4244-0621-8;
S. 151
- 154.
Kurzfassung englisch:
During the design process of a complex system on chip most time is spent on the verification task. Structural verification is one of the primary strategies for testing. We present a method, where the structural testing effort is minimised. This is based on an algorithm, which identifies a set of linearly independent paths of a control flow graph together with a shortest path search. An example is given, where the effort for structural testing can be reduced by more than 40%.
Online-Bibliotheks-Katalog der TU Wien:
http://aleph.ub.tuwien.ac.at/F?base=tuw01&func=find-c&ccl_term=AC06586268
Elektronische Version der Publikation:
http://publik.tuwien.ac.at/files/pub-et_11481.pdf
Erstellt aus der Publikationsdatenbank der Technischen Universität Wien.