Talks and Poster Presentations (with Proceedings-Entry):
M. Holzer, B. Knerr, M. Rupp:
"Structural Verification in Minimal Time";
Talk: International Symposium on System-on-Chip (SOC),
- 11-16-2006; in: "International Symposium on System-on-Chip",
During the design process of a complex system on chip most time is spent on the verification task. Structural verification is one of the primary strategies for testing. We present a method, where the structural testing effort is minimised. This is based on an algorithm, which identifies a set of linearly independent paths of a control flow graph together with a shortest path search. An example is given, where the effort for structural testing can be reduced by more than 40%.
Online library catalogue of the TU Vienna:
Electronic version of the publication:
Created from the Publication Database of the Vienna University of Technology.