Talks and Poster Presentations (with Proceedings-Entry):

F. Weiss, H.D. Wohlmuth, D. Kehrer, A.L. Scholtz:
"A 24-Gb/s 2 7-1 Pseudo Random Bit Sequence Generator IC in 0.13 m Bulk CMOS";
Talk: European Solid-State Circuit Conference, Montreux, Schweiz; 09-19-2006 - 09-21-2006; in: "ESSCIRC 2006 Proceedings", (2006), 1-4244-0303-4; 468 - 471.

English abstract:
This work presents a 24 Gb/s pseudo random bit sequence (PRBS) generator with a sequence length of 2^7-1. The circuit uses an interleaved linear feedback shift register and multiplexing architecture. An output voltage swing of 280 mVpp is achieved for 24 Gb/s data rate and 390 mVpp for 10 Gb/s. The circuit features a trigger output which allows to trigger the eye or the sequence pattern. The circuit is manufactured in 0.13 ?m bulk CMOS technology and draws 183 mA at 1.5 V supply voltage.

Online library catalogue of the TU Vienna:

Electronic version of the publication:

Created from the Publication Database of the Vienna University of Technology.