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C. Angerer:
"A Digital Receiver Architecture for RFID Readers";
Talk: IEEE 3rd International Symposium on Industrial Embedded Systems - SIES 2008, Frankreich; 2008-06-11 - 2008-06-13; in: "IEEE 3rd International Symposium on Industrial Embedded Systems - SIES 2008 - Book of Proceedings", (2008), ISBN: 978-1-4244-1995-1; 97 - 102.

This paper presents a digital receiver architecture
for an RFID reader. The main challenge in RFID reader design
is the detection of the backscattered signals from the tags, which
can be severely complicated due to the largely varying scale of
possible receive powers. Furthermore noise, which power depends
on the environment can degrade the detection performance. The
detection of the signals of the tags is additionally impeded by
the very strong self interference at the reader with the carrier it
needs to send in order to supply the tags with energy. To fight
these various disturbances, a new RFID receiver algorithm is
proposed, that sets its decision threshold adaptively, depending
on the strength of the input signal, the noise power at the
receiver and the extent of the carrier interference. This is the
first algorithm for signal detection in RFID, setting its threshold
accordingly to the environmental conditions, and thus leading
to near optimum performance. Details of the implementation of
the digital receiver architecture on an FPGA are introduced.
Bit error ratio measurements have been carried out to rate the
receivers performance, which have never been shown before for
RFID receivers. Presented measurement results substantiate the
performance of the suggested algorithm.

RFID, rapid prototyping, testbed, receiver architecture, FPGA

http://dx.doi.org/10.1109/SIES.2008.4577685

http://publik.tuwien.ac.at/files/pub-et_13811.pdf