Vorträge und Posterpräsentationen (mit Tagungsband-Eintrag):
P. Atanassov, P. Puschner, R. Kirner:
"Using Real Hardware to Create an Accurate Timing Model for Execution-Time Analysis";
Vortrag: IEEE Workshop on Real-Time Embedded Systems,
London, United Kingdom;
03.12.2001; in: "Proceedings of the IEEE International Workshop on Real-Time Embeeded Systems (in conjunction with 22nd IEEE RTSS 2001)",
(2001).
Kurzfassung englisch:
In this paper we describe the construction of a safe and tight timing model of the Infineon C167 processor. We performed systematic measurements to assess the execution time of single instructions and of instruction sequences. All timing measurements were performed on real hardware, not on an emulator. The accurate timing model was implemented in a tool for static WCET analysis. The WCET estimates made by the tool for several benchmark programs are safe and remarkably tight.
Elektronische Version der Publikation:
http://www.vmars.tuwien.ac.at/php/pserver/extern/docdetail.php?DID=804&viewmode=published&year=2001
Erstellt aus der Publikationsdatenbank der Technischen Universität Wien.