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T. Kottke, A. Steininger:
"A Generic Dual-Core Architecture";
Vortrag: 7th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2004), Stara Lesna, Slovakia; 18.04.2004 - 21.04.2004; in: "7th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2004)", (2004), ISBN: 80-969117-9-1; S. 159 - 166.

In this paper we will propose a frame for the implementation of a dual core processor. The proposed frame is generic in the sense that it allows a fail-silent processor to be constructed using two instances of any arbitrary standard processor core. No changes in these standard cores are necessary, in fact the standard cores can be considered as black box (like in case of IP modules, e.g.). The only requirement on the processor core is that it should provide a Harvard architecture. By means of an analysis of the proposed architecture’s components with respect to common failure modes and potential single points of failure we argue that any single fault can be tolerated. As a proof of feasibility we apply our approach to the processor core SPEAR. In an experimental study performed on this dual core SPEAR processor we prove the fault-tolerance properties of our architectural framework.

http://aleph.ub.tuwien.ac.at/F?base=tuw01&func=find-c&ccl_term=AC04968477

Projektleitung Andreas Steininger:
Bosch