Talks and Poster Presentations (with Proceedings-Entry):

T. Kottke, A. Steininger:
"A Dual Core Architecture with Error Containment";
Talk: East-West Design & Test International Workshop(EWDTW´04), Yalta-Alushta, Crimea, Ukraine; 2004-09-23 - 2004-09-26; in: "East-West Design & Test International Workshop", (2004), ISBN: 966-659-088-3; 102 - 108.

English abstract:
Dual core architectures are very attractive for implementing fail-silent processors, since they allow two instances of an off-the-shelf processor core to be combined without changes; in fact the standard cores can be considered as black boxes. For additional coverage of common mode failures such as power supply surges the two cores can be operated with a mutual time shift of several clock cycles. The drawback of the time shift operation is that it introduces an error detection latency, during which erroneous data can pollute external components such as memory or I/O. This paper extends existing approaches in this area by proposing a "dual core error containment concept" to prevent this undesired pollution. By means of a careful analysis of the proposed additional framework components with respect to potential single points of failure we argue that any single fault can be detected. To prove this claim the proposed solution is applied to an actual design and extensive fault injection experiments are performed. The results demonstrate that the proposed concept indeed allows to detect all malicious errors within the dual core before or during their propagation to the memory or I/O modules.

Related Projects:
Project Head Andreas Steininger:

Created from the Publication Database of the Vienna University of Technology.