Scientific Reports:

A. Steininger, T. Handl, G. Fuchs:
"EPOCAL - Exploring the Potential of Code Alternation Logic";
Report for Research Report 71/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004.

English abstract:
Digital systems have become an integral part of our daily lives; they appear in the guise of the PC at work as well as the cellular phone or a controller in the car. They are the most important innovation driver and represent a virtually immeasurable market. According to the traditional rules digital systems are designed in a synchronous style, i.e. all activities are under the control of a central clock. Technological progress has facilitated a rapid increase of the clock rate and to the same extent of performance as well. Due to several reasons, however, this increase of the clock rates cannot be sustained in the future, and even today substantial efforts are made to maintain the synchronous paradigm for GHz clocks in the physical implementation. Asynchronous design styles that have been viewed as inefficient in the past are now being considered as potential alternatives. In addition, one of their major benefits, namely low power consumption, is becoming a crucial issue in today’s countless low-power applications. Our research group at the Vienna University of Technology has recently developed a novel asynchronous design method that appeared extremely promising in our first investigations. This so-called "Code Alternation Logic (CAL)" is based on the conceptually very elegant "delay insenstitve model". A delay insensitive circuit will work even under extreme environmental conditions and facilitates easy migration of process technology. It is the aim of the project EPOCAL to close residual gaps in the concept and develop a reference implementation that illustrates the benefits of the CAL approach. For this purpose an existing 16-bit microprocessor design shall be transformed to CAL, and both the synchronous and the asynchronous microprocessor be implemented together on an ASIC. This implementation will not only allow to prove the applicability of CAL for complex digital circuits, it will also facilitate a direct comparison of the properties of synchronous and asynchronous (CAL based) implementation with respect to performance, robustness, real-time behaviour, power consumption and further application related parameters. Finally the ASIC shall be embedded in a demonstrator application that allows us to convince industrial partners of the advantages of CAL and attract them for further development.

Electronic version of the publication:

Created from the Publication Database of the Vienna University of Technology.