A. Steininger, M. Delvai, W. Huber:
"Code Alternation Logic -- A Novel and Efficient Method for Delay-Insensitive Asynchronous Circuits";
Report for Research Report 84/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria;
As the clock rates of synchronous chip designs are facing physical limits, asynchronous design methods gain increasing interest. Among these the "delay insensitive" timing model is particularly appealing, since it allows to guarantee the correct function completely independent of implementation related delays. We propose CAL, a new coding scheme for delay insensitive digital circuits that offers all advantages of the known state based (return to zero, RTZ) coding techniques. In contrast to existing RTZ-approaches CAL does not require an explicit unproductive "zero" code between any two data words for synchronization. Instead, CAL uses an alternating code set to represent logic states, which allows one data word to be directly followed by the next one. Obviously this doubles performance while halving energy consumption. While these features make CAL comparable to non- return to zero (NRZ) based techniques, we show that design and hardware implementation for CAL are signi»cantly cheaper and easier than that of NRZ approaches.
Electronic version of the publication:
Created from the Publication Database of the Vienna University of Technology.