W. Huber, A. Steininger, M. Delvai:
"Delay Insensitive Asychronous Pipeline Implementation for Code Alternation Logic";
Report for Research Report 85/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria;
Virtually all asynchronous design techniques employ pipelining to structure the data path. The classical micropipeline architecture as introduced by Sutherland provides a generic solution to this problem; it is, how- ever, not a delay insensitive approach, since handshak- ing is based on delay elements. So the question arises, whether it is possible to modify this principle and com- bine it with another method such that the resulting ar- chitecture is indeed delay insensitive. In this paper we investigate this question at the exam- ple of CAL, a design method also known as four phase logic. We propose and optimize different pipeline im- plementations and discuss their respective merits and drawbacks along with simulation results and implemen- tation experiences.
Electronic version of the publication:
Created from the Publication Database of the Vienna University of Technology.