T. Kottke, A. Steininger:
"A Reconfigurable Generic Dual Core Architecture";
Report for Research Report 99/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria;
In this paper we proposes a generic frame for the implementation of a dual-core processor with two operational modes. One operation mode is the safety mode which allows to run the two cores in lock step in a classical master/checker fashion. A clock delay of 1.5 clock cycles between master and checker establishes the temporal redundancy to minimize the potential for common mode faults. The second operation mode allows a parallel execution of different instruction streams on the two cores in a multiprocessor fashion. The possibility to dynamically switch between the two modes allows for an efficient utilization of the duplicated core. In this paper we propose an implementation of such a generic frame that can be applied in conjunction with virtually any standard processor core. We introduce the functional units required for this implementation and perform a systematic failure analysis for the safety mode and the mode switching procedure. Experimental fault injection confirms that our reconfigurable architecture indeed provides the same fail safe properties as the classical master/checker architecture.
Electronic version of the publication:
Created from the Publication Database of the Vienna University of Technology.