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M. Delvai, G. Fuchs, T. Handl, W. Huber, A. Steininger:
"Design of an Asynchronous Microprocessor with Four-State Logic";
Talk: Austrochip, Wien; 2005-10-06; in: "Austrochip 2005", (2005), 105 - 112.

With the ever increasing clock rates the conceptual drawbacks of the synchronous design paradigm are becoming more and more painful. Asynchronous design methods promise to be attractive alternatives, however, many questions in context with their practical applicability still need to be addressed. In this paper we review the differences between synchronous and asynchronous logic and present the design and implementation of our asynchronous processor ASPEAR. In particular we detail the design method and the design flow we have applied for the ASPEAR implementation and discuss specific problems we have encountered. Finally, we summarize the results of investigations we have performed on ASPEAR.

http://aleph.ub.tuwien.ac.at/F?base=tuw01&func=find-c&ccl_term=AC05936325