Diploma and Master Theses (authored and supervised):
"An Asynchronous Hardware Design for Distributed Tick Generation";
Supervisor: A. Steininger;
Technische Informatik, E182/2,
final examination: 2006.
The main topic of this diploma thesis is the hardware-implementation of a distributed fault tolerant algorithm, which generates local (clock-)ticks that are, within a certain precision, synchronous to each other. This work is done in the context of DARTS (Distributed Algorithms for Robust Tick Synchronization) and is funded by the BMVIT within the scope of FIT-IT. DARTS is a joint project between the Institute for Computer Engineering - Embedded Computing Systems Group at the Vienna University of Technology and Austrian Aerospace GmbH. The motivation of the project is to avoid the use of global clock signals and the related disadvantages: Single nodes generate local tick-transitions in dependence upon each other. The underlying distributed algorithm assures that these transitions occur within a certain but evaluable time span at all (non-faulty) nodes. Therefore, the different clocks do not drift apart, which makes explicit resynchronization obsolete. Based on the algorithm, functional units are identified and modified such that a high-performance and area-saving hardware realization is feasible. Since the logic is designed to generate a clock signal, it has to meet asynchronous design paradigms. Thereby, one of the most important gates is the Muller- C-Element, which is a basic part of various asynchronous modules like, for example, micropipelines. This work describes two different hardware implementations: On the one hand, there is a non-optimized design for an FPGA board, which is used to test the correct behavior of the underlying algorithm. In addition, an area and speed-optimized ASIC design is developed, which shall form the basis for the fabrication of a prototype. Thereby, the logic needs to meet several constraints which can only be fulfilled by clever place and route.
Project Head Andreas Steininger:
Verteilte Algorithmen für robuste Takt-Synchronisation
Created from the Publication Database of the Vienna University of Technology.