Talks and Poster Presentations (with Proceedings-Entry):
G. Fuchs, M Függer, A. Steininger, F. Zangerl:
"Analysis of Constraints in a Fault-Tolerant Distributed Clock Generation Scheme";
Talk: 3rd International Workshop on Dependable Embedded Systems,
2006-10-01; in: "WDES 2006 3rd Workshop on Dependable Embedded Systems",
In the course of our DARTS project we are pursuing a new fault-tolerant clock generation scheme targeted at Systems-on-Chip. The idea is to take existing distributed fault-tolerant partially synchronous algorithms and adapt them to the peculiarities of hardware. In this paper we take a closer look at general constraints that arise from these adaptations and provide formal proofs for their correctness.
Online library catalogue of the TU Vienna:
Project Head Andreas Steininger:
Verteilte Algorithmen für robuste Takt-Synchronisation
Created from the Publication Database of the Vienna University of Technology.