Talks and Poster Presentations (with Proceedings-Entry):
A. Steininger, T. Handl, G. Fuchs, F. Zangerl:
"Testing the Hardware Implementation of a Distributed Clock Generation Algorithm for SoCs";
Talk: East-West Design & Test International Workshop (EWDTW'06),
Sochi (invited);
2006-09-15
- 2006-09-19; in: "East-West Design & Test International Workshop",
(2006),
59
- 64.
English abstract:
This paper presents our test strategy for a hardware unit that is at the heart of a fault-tolerant distributed clock generation concept for a System-on-Chip (SoC). The specific problem with testing this unit lies in its asynchronous but still sequential nature. We outline how we still manage to achieve the required test coverage for this unconventional circuit on a synchronous tester, while minimizing area overhead, performance penalties and test time.
Online library catalogue of the TU Vienna:
http://aleph.ub.tuwien.ac.at/F?base=tuw01&func=find-c&ccl_term=AC06586906
Related Projects:
Project Head Andreas Steininger:
Verteilte Algorithmen für robuste Takt-Synchronisation
Created from the Publication Database of the Vienna University of Technology.