Talks and Poster Presentations (with Proceedings-Entry):
M Függer, U. Schmid, G. Fuchs, G. Kempf:
"Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip";
Talk: European Dependable Computing Conference,
- 2006-10-20; in: "EDCC-6",
This paper introduces a simple fault-tolerant tick generation algorithm based on Srikanth & Toueg's consistent broadcast primitive that can be directly implemented in VLSI using asynchronous digital logic. The need for adaption originates from two peculiarities of hardware implementations: (i) Fine-grained parallel asynchronous computations, which undermines the concept of atomic steps common to all distributed computing models, and (ii) very limited resources, which makes even apparently simple operations prohibitively costly. We prove that the resulting algorithm is correct, and derive performance metrics like worst case precision and accuracy. Moreover, we outline the major building blocks of our synthesizable VHDL implementation and provide some measurement results from our FPGA prototype. Our results hence provide the required basis for investigating robust alternatives to synchronous clocking in VLSI Systems-on-Chip and similar applications.
Online library catalogue of the TU Vienna:
Project Head Andreas Steininger:
Verteilte Algorithmen für robuste Takt-Synchronisation
Created from the Publication Database of the Vienna University of Technology.