[Back]

M. Ferringer, G. Fuchs, A. Steininger, G. Kempf:
"VLSI Implementation of a Fault-Tolerant Distributed Clock Generation";
Talk: International Symp. on Defect and Fault Tolerance in VLSI-Systems, Arlington; 2006-10-04 - 2006-10-06; in: "The 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems", (2006), 563 - 571.

In this paper we will introduce a novel approach for the on-chip generation of a fault-tolerant clock. We will motivate why it becomes more and more desirable to provide VLSI circuits with fault-tolerant clocking methods and how this fault tolerance can be achieved. The proposed clock generation method is based on the adaptation of a well known distributed clock synchronization algorithm which has been adapted for hardware implementation. We will present the underlying algorithm, point out the difficulties for the hardware implementation and will provide a detailed description of the resulting VLSI implementation. To emphasize the feasibility of the proposed fault-tolerant clock generation method we also present some measurement results from a prototype implementation.

http://aleph.ub.tuwien.ac.at/F?base=tuw01&func=find-c&ccl_term=AC06586911

Project Head Andreas Steininger:
Verteilte Algorithmen für robuste Takt-Synchronisation