Talks and Poster Presentations (with Proceedings-Entry):
C. El Salloum, A. Steininger, P Tummeltshammer:
"Recovery Mechanisms for Dual Core Architectures";
Talk: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT ),
Washington DC, USA;
- 2006-10-06; in: "21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006, Proceedings",
Dual core architectures are commonly used to establish fault tolerance on the node level. To be able to treat the cores as black boxes, comparison is performed for the outputs only. As a consequence, however, no diagnostic information is available, and hence error handling comes down to a reset of both cores. The strategy we propose in this paper allows a more sophisticated error handling. It is based on the following steps: (1) Identi cation of those registers that are actually relevant for recovering the last known correct core state. (2) Protection of these registers by additional comparators. (3) Use of the trap mechanism for recovering a consistent state of the complete core. (4) (Optional) provision of rollback capability for the relevant registers in order to relax the critical path constraints. In the paper we discuss and motivate these individual steps and put them into context. In many cases the speed-up we gain for the recovery will be suf cient for using a dual-core as a fail-operational rather than a fail-silent component with respects to transient faults.
Online library catalogue of the TU Vienna:
Project Head Andreas Steininger:
Created from the Publication Database of the Vienna University of Technology.