Talks and Poster Presentations (with Proceedings-Entry):

T. Handl, A. Steininger, G. Kempf:
"An Efficient Test Strategy for a Fault-Tolerant Clock Generator for Systems-on-Chip";
Talk: 19. ITG/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Errlangen; 2007-03-11 - 2007-03-13; in: "19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (2007), 66 - 70.

English abstract:
We describe the test concept for a clock genera- tion unit that implements one instance of a distributed agreement algorithm in hardware. The challenge of testing this unit lies in its asynchronous nature. We propose a suitable partitioning of the self-timed circuit and the introduction of two scan chains whose opera- tion is carefully interlocked. In this way we can achieve a coverage of 100% for single stuck-at faults with very low overheads in term of speed penalty and test pins.

Related Projects:
Project Head Andreas Steininger:
Verteilte Algorithmen für robuste Takt-Synchronisation

Created from the Publication Database of the Vienna University of Technology.