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C. El Salloum, R. Obermaisser, B. Huber, H. Paulitsch, H. Kopetz:
"A time-triggered system-on-a-chip architecture with integrated support for diagnosis";
Vortrag: Design, Automation and Test in Europe Conference (DATE'07), Nice, France; 16.04.2007 - 20.04.2007; in: "Workshop Digest, Diagnostic Services in Network-on-Chips", DATE'07, (2007), Paper-Nr. 3 (Seite 136f), 2 S.

It is the objective of the presented SoC architecture to provide a
predictable integrated execution environment for component-based
design with integrated diagnostic mechanisms for many different
types of embedded applications (e.g., automotive, avionics, consumer
electronics). The integrated diagnostic mechanisms of the
SoC architecture facilitate the identification of faulty IP blocks and
the discrimination between transient and permanent faults. By
exploiting the inherent fault isolation and the global time base of
the time-triggered Network-on-a-Chip, a diagnostic unit can pinpoint
the micro components that are responsible for an anomalous
system behavior. For this purpose, the diagnostic unit correlates
failure indication messages along the dimensions of time and
space.