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Zeitschriftenartikel:

S. Farfeleder, A. Krall, N. Horspool:
"Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures";
Journal of Systems Architecture, 53 (2007), 8; S. 501 - 510.



Kurzfassung englisch:
Emulation of one architecture on another is useful when the architecture is under design, when software must be ported to a new platform or is being developed for systems which are still under development, or for embedded systems that insufficient resources to support the software development process. Emulation using an interpreter is typically slower than normal execution by up to 3 orders of magnitude. Our approach instead translates the program from the original architecture to another architecture while faithfully preserving its semantics at the lowest level. The emulation speeds are comparable to, and often faster than, programs running on the original architecture. Partial evaluation of architectural features is used to achieve such impressive performance, while permitting accurate statistics collection. Accuracy is at the level of the number of clock cycles spent executing each instruction (hence the description cycle-accurate).

Schlagworte:
Compiled emulation, Instruction set emulator, Interpreter, Pipelined VLIW architecture


"Offizielle" elektronische Version der Publikation (entsprechend ihrem Digital Object Identifier - DOI)
http://dx.doi.org/10.1016/j.sysarc.2006.11.003

Elektronische Version der Publikation:
http://publik.tuwien.ac.at/files/pub-inf_5029.pdf


Erstellt aus der Publikationsdatenbank der Technischen Universitšt Wien.