Talks and Poster Presentations (with Proceedings-Entry):
"A Time-Triggered Network-on-Chip";
Talk: 17th International Conference on Field Programmable Logic and Applications (FPL2007),
- 2007-08-29; in: "2007 International Conference on Field Programmable Logic and Applications (FPL)",
A Time-Triggered Network-on-Chip
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
27-29 Aug. 2007 Page(s):377 - 382
In this paper we propose a time-triggered network-on-chip (NoC) for on-chip real-time systems. The NoC provides time predictable on-and off-chip communication, a mandatory feature for dependable real-time systems. A regular structured NoC with a pseudo-static communication schedule allows for a high bandwidth. In this paper we argue for a simple, time-triggered NoC structure to achieve maximum bandwidth. We have implemented the proposed TT-NoC in a low-cost FPGA. The base bandwidth is 29 Gbit/s and the peak bandwidth 230 Gbit/s for eight nodes. The idea is in line with current on-chip multiprocessor designs, such as the Cell processor. The simple design of the network and the network interface easies certification of the proposed NoC for safety critical applications.
"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
Created from the Publication Database of the Vienna University of Technology.