Talks and Poster Presentations (with Proceedings-Entry):
R. Kirner, M. Schoeberl:
"Modeling the function cache for worst-case execution time analysis";
Talk: 44th Design Automation Conference (DAC'07),
San Diego, California/USA;
2007-06-04
- 2007-06-08; in: "Proceedings of the 44th annual conference on Design automation",
ACM,
(2007),
ISBN: 978-1-59593-627-1;
471
- 476.
English abstract:
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function caches, a special kind of instruction cache that caches whole functions only. This cache was designed with the aim to be more predictable for the worst-case than existing instruction caches. Within this paper we developed a cache analysis technique for the function cache. One of the new concepts of this analysis technique is the local persistence analysis, which allows to precisely model the function cache.
Keywords:
WCET, cache analysis, function cache, worst-case execution time
"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
http://dx.doi.org/10.1145/1278480.1278603
Created from the Publication Database of the Vienna University of Technology.