Talks and Poster Presentations (with Proceedings-Entry):
J. Grahsl, T. Handl, A. Steininger, G. Kempf:
"SAFE - A Scalable Environment for Automated Transistor Level Fault Effect Analysis";
2007-10-11; in: "Austrochip - Workshop on Microelectronics",
As recent trends within the testing community show, the shortcomings of the classical gate level stuck-at fault model evolve into increasingly severe issues, especially with respect to coverage and fault effect analysis. In addition, this model is not applicable to emerging design styles like transition signaling and self-timed circuits, where information is encoded both in the value and time domain. To cope with these insufficiencies, testing at transistor level can be envisioned to examine circuits much more in-depth. However, due to the higher costs and expenditure of time, this method seemed inferior to stuck-at fault testing to industrial practice until now. In this paper, we will (i) introduce a classification of transistor level faults appropriate for efficient testing and (ii) present a framework to perform transistor level fault effect analysis - based upon this classification - automatically and thus with limited efforts.
Project Head Andreas Steininger:
Verteilte Algorithmen für robuste Takt-Synchronisation
Created from the Publication Database of the Vienna University of Technology.