Vorträge und Posterpräsentationen (mit Tagungsband-Eintrag):
T. Handl, A. Steininger, G. Kempf:
"Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit";
Vortrag: International Design and Test Workshop (IDT),
Kairo;
16.12.2007
- 18.12.2007; in: "Proceedings IDT'07 - The Second International Design and Test Workshop",
(2007),
S. 115
- 119.
Kurzfassung englisch:
We describe the test concept for a clock genera- tion unit that implements one instance of a distributed agreement algorithm in hardware. The challenge of testing this unit lies in its asynchronous nature. We propose a suitable partitioning of the self-timed circuit and the introduction of two scan chains whose opera- tion is carefully interlocked. In this way we can achieve a coverage of 100% for single stuck-at faults with very low overheads in term of speed penalty and test pins.
Zugeordnete Projekte:
Projektleitung Andreas Steininger:
Verteilte Algorithmen für robuste Takt-Synchronisation
Erstellt aus der Publikationsdatenbank der Technischen Universität Wien.