Talks and Poster Presentations (with Proceedings-Entry):
T. Handl, A. Steininger, G. Kempf:
"Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit";
Talk: International Design and Test Workshop (IDT),
- 2007-12-18; in: "Proceedings IDT'07 - The Second International Design and Test Workshop",
We describe the test concept for a clock genera- tion unit that implements one instance of a distributed agreement algorithm in hardware. The challenge of testing this unit lies in its asynchronous nature. We propose a suitable partitioning of the self-timed circuit and the introduction of two scan chains whose opera- tion is carefully interlocked. In this way we can achieve a coverage of 100% for single stuck-at faults with very low overheads in term of speed penalty and test pins.
Project Head Andreas Steininger:
Verteilte Algorithmen für robuste Takt-Synchronisation
Created from the Publication Database of the Vienna University of Technology.