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C. Angerer, O. Cevan, L. Fauster, Y. Huang, B. Huber, V. Legourski, S. Pirker, T. Polzer, D. Reichhard, D. Rigler, A. Schuster, B. Weirich, P Tummeltshammer, M. Delvai:
"Exploring Hardware Software Partitioning on the Example of a Face Recognition System";
Poster: Austrochip, Graz; 2007-10-11; in: "Austrochip - Workshop on Microelectronics", (2007), ISBN: 978-3-902465-87-0; 121 - 127.

Today´s FPGAs offer a great amount of configurability and therefore allow for completely new possibilities and challenges in system design. The partitioning of a design into hardware and software, which is done in the Hardware Software Codesign, is a delicate process which by choosing an unfavorable partitioning may lead to poor results.
In this paper we investigate the impact of different hardware software partitioning strategies on a face verification system. Several groups of students had to implement such a system, whereas the hardware software partitioning was not a priori given, but had to be done by each group individually. Each implementation was evaluated by comparing several system parameters such as power consumption, performance, number of instructions, etc. At the end of the paper we compare all implementations and discuss the impact of the partitioning decisions.