Talks and Poster Presentations (with Proceedings-Entry):
"SimpCon - a Simple and Efficient SoC Interconnect";
2007-10-11; in: "Proceedings of the 15th Austrian Workhop on Microelectronics, Austrochip 2007",
IEEE Austria Section / TU Graz,
To build a system-on-chip (SoC) a common interface standard is necessary to connect ready-to-use components (IPs) from different vendors. Today several SoC interconnect standards, such as AMBA, Wishbone, OPB, and Avalon, are in use. We show in this paper that those standards have a common drawback for on-chip interconnections: They are built on the model of a common back-plane bus that does not fit very well for on-chip interconnections. We provide a new, simple on-chip interconnect specification for the well accepted master/slave model. It is intended to provide pipelined access to devices such as on-chip peripherals and on-chip memory controller with minimum hardware resources.
Created from the Publication Database of the Vienna University of Technology.