Talks and Poster Presentations (with Proceedings-Entry):
A. Kadlec, R. Kirner:
"On the Difficulty of Building a Precise Timing Model for Real-Time Programming";
Talk: 14. Kolloquium "Programmiersprachen und Grundlagen der Programmierung (KPS'07)",
Timmendorfer Strand, Germany;
- 2007-10-12; in: "14. Kolloquium Programmiersprachen und Grundlagen der Programmierung",
For real-time computing it is important to know the worst-case execution time (WCET) of all time-critical software operations in order to ensure timeliness of the system. The calculation of a precise upper bound of the WCET relies on the availability of an adequate timing model of the target hardware. However, WCET calculation is challenged by the increasing complexity of the processors used in real-time computing. Within this article we explore the different mechanisms of modern processors that lead to complex timing models. We explore the different types of memory elements of a processor that resemble the state of the processor. Further, we compare the consequences of offline and online (during execution) code optimization. The main consequence of this hardware exploration is that real-time computing needs a hardware/software co-design approach to improve temporal predictability of the computation.
Electronic version of the publication:
Created from the Publication Database of the Vienna University of Technology.