Talks and Poster Presentations (with Proceedings-Entry):
F. Seitner, R. Schreier, M. Bleyer, M. Gelautz:
"A high-level simulator for the H.264/AVC decoding process in multi-core systems";
Talk: SPIE IS&T Electronic Imaging Conference,
- 2008-01-31; in: "Proceedings of SPIE, Multimedia on Mobile Devices 2008",
H.264 as a new-generation video coding algorithm is becoming increasingly important for international broadcasting standards such as DVB-H and DMB. In comparison to its predecessors MPEG-2 and
MEPG-4 SP/ASP, H.264 achieves improved compression efficiency at the cost of increased computational complexity. Real-time execution of the H.264 decoding process poses a large challenge on mobile devices due to low processing capabilities. Multi-core systems provide an elegant and power-efficient solution to overcome this performance limitation. However, efficiently distributing the video algorithm among multiple processing units is a non-trivial task. It requires detailed knowledge about the algorithmic complexity, dynamic variations and inter-dependencies between functional blocks. The objective of this paper is an investigation on the dynamic
behavior of the H.264 decoding process and on the interaction between the main decoding tasks in the context of multi-core environments. We use an H.264 decoder model to investigate the efficiency of a decoding system under various conditions (e.g. different FIFO buffer sizes, bitstreams, coding features and bitrates). The gained insights are finally used to optimize the runtime behavior of a multi-core decoding system and to find a good
trade-off between core usage and buffer sizes.
Multi-core, video, decoding, H.264/AVC, modeling
"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
Electronic version of the publication:
Created from the Publication Database of the Vienna University of Technology.