Talks and Poster Presentations (with Proceedings-Entry):
G. Fuchs, M Függer, U. Schmid, A. Steininger:
"Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip";
Talk: 11th EUROMICRO Conference on Digital System Design (DSD 2008),
- 2008-09-05; in: "11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008.",
Systems on chip (SoC) have much in common with traditional (networked) distributed systems in that they consist of largely independent components with dedicated communication interfaces. Therefore the adoption of classic distributed algorithms for SoCs suggests itself. The implementation complexity of these algorithms, however, significantly depends on the underlying failure models. In traditional software-based solutions this is normally not an issue, such that the most unconstrained, namely the Byzantine, failure model is often applied here. Our case study of a hardware implemented tick synchronization algorithm shows, however, that in an SoC-implementation substantial hardware savings can result from restricting the failure model to benign failures (omissions, crashes). On the downside, it turns out that such restricted failure models have a fairly poor coverage with respect to the hardware faults occurring in practice, and that additional measures to enforce these restrictions may entail an implementation overhead that outweighs the gain obtained in the implementation of a simpler algorithm. As a remedy we investigate the potential of failure transformation in this context and show that this technique may indeed yield an optimized overall solution.
"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
Project Head Andreas Steininger:
Verteilte Algorithmen für robuste Takt-Synchronisation
Created from the Publication Database of the Vienna University of Technology.