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M. Ibrahim, M. Rupp, H. Fahmy:
"Power Estimation Methodology for VLIW Digital Signal Processors";
Poster: Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, USA; 26.10.2008 - 29.10.2008; in: "Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers", (2008).

Abstract-In this contribution the modeling of power consumption
for the VLIW processor TMS320C6416T is presented
taking into account typical software algorithms in signal and
image processing. The modeling is performed at the functional
level making this approach distinctly different from other modeling
approaches in low level technique. This means that the
power consumption can be identified at an early stage in the
design process, enabling the designer to explore different hardware
architectures and software algorithms. Some typical signal
and image processing algorithms are used for the purpose of
validating the proposed model. The estimated power consumption
is compared to the physically measured power consumption,
achieving a very low resulting average estimation error of 1.05%
and a maximum estimation error of only 3.3%

Power Estimations, VLIW, DSP, Power-Modeling

http://publik.tuwien.ac.at/files/PubDat_169593.pdf

Projektleitung Markus Rupp:
Embedded Computer Vision