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C. Pitter, M. Schoeberl:
"Performance Evaluation of a Java Chip-Multiprocessor";
Vortrag: SIES´2008 Third international symposium on industrial embedded systems, Montpellier - La Grande Motte, France; 11.08.2008 - 13.08.2008; in: "SIES´2008 Third international symposium on industrial embedded systems", (2008), ISBN: 978-1-4244-1995-1; S. 34 - 42.

Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-memory multiprocessor and consists of up to 8 Java Optimized Processor (JOP) cores, an arbitration control device, and a global shared memory. All components are interconnected with a system-on-chip bus. This paper focuses on the performance evaluation of different hardware configurations of the multicore system. Therefore, we vary the instruction cache sizes, the number of processors and the memory bandwidth. Within our experiments, we measure the performance by running three benchmarks on real hardware: an embedded application from industry, a computationally intensive matrix multiplication and a synthetic benchmark that continuously accesses a shared data structure. Two different field-programmable gate arrays are used for the presented experiments. Our results illustrate the promises and limits of the proposed multiprocessor architecture concerning synchronization, memory bandwidth and caching. Furthermore, we compare the performance and size of JopCMP with a complex Java processor.

http://dx.doi.org/10.1109/SIES.2008.4577678