Talks and Poster Presentations (with Proceedings-Entry):

R. Obermaisser, H. Kraut, C. El Salloum:
"A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR";
Talk: Seventh European Dependable Computing Conference (EDCC-7), Kaunas, Lithuania; 2008-05-07 - 2008-05-09; in: "Seventh European Dependable Computing Conference (EDCC-7)", IEEE Computer Society, (2008), ISBN: 978-0-7695-3138-0; 123 - 134.

English abstract:
The ongoing technological advances in the semiconductor
industry make Multi-Processor System-on-a-Chips
(MPSoCs) more attractive, because uniprocessor solutions
do not scale satisfactorily with increasing transistor counts.
In conjunction with the increasing rates of transient faults in
logic and memory associated with the continuous reduction
of feature sizes, this situation creates the need for novel MPSoC
architectures. This paper introduces such an architecture,
which supports the integration of multiple, heterogeneous
IP cores that are interconnected by a time-triggered
Network-on-a-Chip (NoC). Through its inherent fault isolation
and determinism, the proposed MPSoC provides the
basis for fault tolerance using Triple Modular Redundancy
(TMR). On-chip TMR improves the reliability of a MPSoC,
e.g., by tolerating a transient fault in one of three replicated
IP cores. Off-chip TMR with three MPSoCs can be
used in the development of ultra-dependable applications
(e.g., X-by-wire), where the reliability requirements exceed
the reliability that is achievable using a single MPSoC. The
paper quantifies the reliability benefits of the proposed MPSoC
architecture by means of reliability modeling. These
results demonstrate that the combination of on-chip and offchip
TMR contributes towards building more dependable
distributed embedded real-time systems.

"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)

Created from the Publication Database of the Vienna University of Technology.