Talks and Poster Presentations (without Proceedings-Entry):

A. Fellnhofer, A. Krall, D. Riegler:
"Dynamic Binary Translation for Generation of Cycle Accurate Architecture Simulators";
Talk: Emerging Uses and Paradigms for Dynamic Binary Translation, Schloss Dagstuhl (invited); 2008-10-26 - 2008-10-31.

English abstract:
In this talk we discuss our experiences in using the LLVM just-in-time
compiler as code generator in a cycle accurate architecture simulator
for pipelined architectures. The architecture simulator is generated
from an architecture specification in a mostly structural architecture
description language. The simulator contains an interpreter and
dynamically translates first heavy executed basic blocks and later
traces to machine code. Spreading of pipelined instructions over basic
block boundaries is solved by basic block duplication. We present
detailed results for a MIPS and a VLIW simulator. Simulation speeds of
up to 800 MHz on a 2200MHz Athlon 64 processor are reached.

dynamic binary translation,

Created from the Publication Database of the Vienna University of Technology.