Talks and Poster Presentations (with Proceedings-Entry):

J. Grahsl, T. Handl, A. Steininger:
"Exploring the Usefulness of the Gate-level Stuck-at Fault Model for Muller C-Elements";
Poster: 20. GI/ITG/GMM Workshop Testmethoden und Vuverlässigkeit von Schaltungen und Systemen, Wien; 2008-02-24 - 2008-02-26; in: "20. Workshop Testmethoden und Vuverlässigkeit von Schaltungen und Systemen", (2008), 165 - 169.

English abstract:
The stuck-at fault model has proven extremely efficient for
test vector generation in the combinational logic portions of synchronous circuits. Comparatively little, however, is known about its usefulness for testing asynchronous circuits. In this paper we will investigate this point at the example of the Muller C-element, a basic building block in asynchronous designs. Using fault simulation on the circuit level we will determine the coverage of test vector sets that have been derived based on the stuck-at model. We will identify uncovered faults and analyze their origin.

Related Projects:
Project Head Andreas Steininger:
Verteilte Algorithmen für robuste Takt-Synchronisation

Created from the Publication Database of the Vienna University of Technology.